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Fault detection in configurable switched-capacitor filters using transient analysis and dynamic time warping

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Abstract

In this work, we address a low-cost test of switched capacitors filters embedded in configurable analog sections. The proposal improves the Transient Analysis Method (TRAM) by incorporating a similarity measure, dynamic time warping. In this way, we extend TRAM to cases that that initially were not compatible and simplify the test of filters of order higher than two. This paper performs the test evaluation by developing a new simulation model of the addressed system that supports fault injection and simulation. A comparison with experimental data in both normal and faulty behavior validates the model. We consider catastrophic faults in the switches (stuck at open and short) and capacitors (shorts and opens), and deviation faults in the capacitors. The fault simulation results validate the test proposed here.

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Correspondence to Gabriela Peretti.

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Appendix

Appendix

1.1 Opamp simulation model

We developed a simulation model for the op-amps present in the analog sections of the PSoC 1 processor used to establish the performance of the filters. The model is behavioral and uses the information reported by the vendor in the datasheet. The adopted structure allows a balance between the accuracy in the results and the computational costs of the fault simulation campaigns necessary for validating our scheme. It is remarked that the model is a combination of previous formulations done for other authors. For this reason, we explain in this Appendix only the central aspect of the simulation model for the filter.

The characteristics modeled by the op-amp model are: slew rate (SR+ and SR), common-mode rejection (CMRR), gain-bandwidth product (GBW), limitation of the output signal (Vout+ and Vout), offset voltage (Voffset), and open-loop gain (Aol). The resulting topology is depicted in Fig. 11.

Fig. 11
figure 11

Schematic of the op-amp macro model

The input stage provides the op-amp inputs (INN e INP), a DC source (Voffset), and a resistor (Rin) that emulate the input offset voltage and the differential mode input resistance, respectively [19]. The dominant pole characteristic of the op-amp frequency response is implemented with Cp y Rp. The open-loop gain, slew rate, and CMRR are achieved by the interaction between the voltage-controlled current source G1 with Cp and Rp. The transfer characteristic of G1 is composed by adding the common-mode transconductance GCMM (lineal) and the differential mode transconductance (not linear), that Fig. 12 shows.

Fig. 12
figure 12

G1 transfer characteristic

Due to the combined action of GCMM and Gdiff, the voltage in Rp represents the common and differential mode gains. The AGND input allows introducing a DC voltage level that emulates the PSoC block's internal analog reference. In this way, the output signal has a DC level, such in the real circuit. The model represents the slew rate limitation effects by imposing upper and lower limits to the current that Gdiff can deliver (Fig. 12), [20]. This produces that, under fast input violating the op-amp slew rate, Cp charges at a constant rate, emulating the real behavior of the op-amp.

The diodes and the sources named Vpos, and Vneg [19, 20] establish an output signal limiter that allows reproducing the saturation of the real op-amps. The output stage is composed of the output resistance Rout and a unity-gain buffer that avoids load effects in the internal nodes of the model. The source E2 compensates in the voltage limiter, the voltage drops in Rout.

1.2 Generation of the fault-free pattern from the experimental measurement. Source of variability: variations inter-chip.

In Sect. 4.2, the fault-free pattern was acquired from the measurements in one chip under temperature variations. Here we consider a different experiment with variations inter-chip for the second-order filter. The temperature is not modified, and slight variations around 20 °C are allowed.

The experimental setup was similar to the one shown in Fig. 3, without the air heater. Additionally, eight chips configured with the same filter were measured in the Psoc1 Eval board. The DTW threshold was obtained after the process described in Sect. 4.3. The Sett value was 3.5%, without window.

The fault simulation process included catastrophic faults in switches and deviation faults in capacitors of Sect. 5.1. The fault coverage was 100% for catastrophic faults. Table 11 shows the minimal deviations, positive and negative, that can be detected in capacitors. These values are higher than those reported when the source of variation is the temperature, but they are also lower than 5%, showing that the test strategy can be applied when the source of variation is inter-chip.

Table 11 Deviation fault simulations results, second-order filter under inter-chip variations

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Dri, E., Peretti, G. & Romero, E. Fault detection in configurable switched-capacitor filters using transient analysis and dynamic time warping. Analog Integr Circ Sig Process 108, 291–304 (2021). https://doi.org/10.1007/s10470-021-01888-x

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