Abstract
In this work, we address a low-cost test of switched capacitors filters embedded in configurable analog sections. The proposal improves the Transient Analysis Method (TRAM) by incorporating a similarity measure, dynamic time warping. In this way, we extend TRAM to cases that that initially were not compatible and simplify the test of filters of order higher than two. This paper performs the test evaluation by developing a new simulation model of the addressed system that supports fault injection and simulation. A comparison with experimental data in both normal and faulty behavior validates the model. We consider catastrophic faults in the switches (stuck at open and short) and capacitors (shorts and opens), and deviation faults in the capacitors. The fault simulation results validate the test proposed here.
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References
Choi, Y., Lee, Y., Baek, S. H., Lee, S. J., & Kim, J. (2018). CHIMERA: A field-programmable mixed-signal ic with time-domain configurable analog blocks. IEEE Journal of Solid-State Circuits, 53(2), 431–444. https://doi.org/10.1109/JSSC.2017.2757005
Suda, N., Suh, J., Hakim, N., Cao, Y., Bakkaloglu, B. (2016). A 65 nm programmable analog device array (PANDA) for analog circuit emulation. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(2). Doi: https://doi.org/10.1109/TCSI.2015.2512718.
Hasler, J. (2019). Analog architecture complexity theory empowering ultra-low power configurable analog and mixed mode SoC systems. Journal of Low Power Electronics and Applications, 9, 4. https://doi.org/10.3390/jlpea9010004
Schlottmann, C. R., Shapero, S., Nease, S., & Hasler, P. (2012). A digitally enhanced dynamically reconfigurable analog platform for low-power signal processing. IEEE Journal of Solid-State Circuits, 47(9), 2174–2184. https://doi.org/10.1109/JSSC.2012.2194847
Anadigm Inc. (n.d.). http://www.anadigm.com.
Cypress Seminconductor. (2020). Cypress PSoC® and microcontroller (MCU) portfolio roadmap - Q2 2020. Retrieved from https://www.cypress.com/product-roadmaps/cypress-psoc-and-microcontroller-mcu-portfolio-roadmap.
Bushnell, M. L., & Agrawal, V. D. (2004). Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Boston, MA: Springer, US. https://doi.org/10.1007/b117406
Laprovitta, A., Peretti, G., Romero, E., & Mourad, S. (2012). A low-cost configurability test strategy for an embedded analog circuit. Microelectronics Journal, 43(11), 745–755. https://doi.org/10.1016/j.mejo.2012.07.009
Andrade, A., Vieira, G., Balen, T. R., Lubaszewski, M., Azaïs, F., & Renovell, M. (2005). Built-in self-test of global interconnects of field programmable analog arrays. Microelectronics Journal, 36(12), 1112–1123. https://doi.org/10.1016/J.MEJO.2005.06.001
Balen, T. R., Calvano, J. V., Lubaszewski, M. S., & Renovell, M. (2006). Functional Test of Field Programmable Analog Arrays. In: 24th IEEE VLSI Test Symposium (pp. 326–333). Berkeley, CA: IEEE. Doi: https://doi.org/10.1109/VTS.2006.37.
Balen, T. R., Calvano, J. V., Lubaszewski, M. S., & Renovell, M. (2007). Built-in self-test of field programmable analog arrays based on transient response analysis. Journal of Electronic Testing, 23(6), 497–512. https://doi.org/10.1007/s10836-007-5004-8
Dri, E. A., Peretti, G. M., & Romero, E. A. (2020). A low-cost test strategy based on transient response method for embedded reconfigurable filters. International Journal of Electronics. https://doi.org/10.1080/00207217.2020.1793412
Calvano, J. V. V., Alves, V. C., Lubaszewski, M., Castro Alves, V., Lubaszewski, M. (1999). Fault detection in systems with 2nd order dynamics using transient analysis. In: Proceedings 12th Symposium on Integrated Circuits and Systems Design, SBCCI 1999 (pp. 110–114). Natal, RN, Brazil: IEEE. Doi: https://doi.org/10.1109/SBCCI.1999.803099.
Lovay, M. A., Peretti, G. M., & Romero, E. A. (2015). Implementation of an adaptive filter using an evolvable hardware strategy. IEEE Latin America Transactions, 13(4), 927–934. https://doi.org/10.1109/TLA.2015.7106339
Müller, M. (2007). Dynamic Time Warping (DTW). In: Information Retrieval for Music and Motion (pp. 1–313). Springer. https://doi.org/10.1007/978-3-540-74048-3.
Serrà, J., & Arcos, J. L. (2014). Knowledge-based systems an empirical evaluation of similarity measures for time series classification. Knowledge-Based Systems, 67, 305–314. https://doi.org/10.1016/j.knosys.2014.04.035
Ogata, K. (2010). Modern control engineering (5th ed.). . Upper Saddle River, NJ: Prentice-Hall.
Wang, X., Mueen, A., Ding, H., Trajcevski, G., Scheuermann, P., & Keogh, E. (2013). Experimental comparison of representation methods and distance measures for time series data. Data Mining and Knowledge Discovery, 26(2), 275–309. https://doi.org/10.1007/s10618-012-0250-5
Vladimirescu, A. (1994). The Spice book. New York: John Wiley & Sons, Inc.
Hu, C., Leach, D. P., & Chan, S.-P. (1990). An improved macromodel for operational amplifiers. International Journal of Circuit Theory and Applications, 18(2), 189–203. https://doi.org/10.1002/cta.4490180208
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Appendix
Appendix
1.1 Opamp simulation model
We developed a simulation model for the op-amps present in the analog sections of the PSoC 1 processor used to establish the performance of the filters. The model is behavioral and uses the information reported by the vendor in the datasheet. The adopted structure allows a balance between the accuracy in the results and the computational costs of the fault simulation campaigns necessary for validating our scheme. It is remarked that the model is a combination of previous formulations done for other authors. For this reason, we explain in this Appendix only the central aspect of the simulation model for the filter.
The characteristics modeled by the op-amp model are: slew rate (SR+ and SR−), common-mode rejection (CMRR), gain-bandwidth product (GBW), limitation of the output signal (Vout+ and Vout), offset voltage (Voffset), and open-loop gain (Aol). The resulting topology is depicted in Fig. 11.
The input stage provides the op-amp inputs (INN e INP), a DC source (Voffset), and a resistor (Rin) that emulate the input offset voltage and the differential mode input resistance, respectively [19]. The dominant pole characteristic of the op-amp frequency response is implemented with Cp y Rp. The open-loop gain, slew rate, and CMRR are achieved by the interaction between the voltage-controlled current source G1 with Cp and Rp. The transfer characteristic of G1 is composed by adding the common-mode transconductance GCMM (lineal) and the differential mode transconductance (not linear), that Fig. 12 shows.
Due to the combined action of GCMM and Gdiff, the voltage in Rp represents the common and differential mode gains. The AGND input allows introducing a DC voltage level that emulates the PSoC block's internal analog reference. In this way, the output signal has a DC level, such in the real circuit. The model represents the slew rate limitation effects by imposing upper and lower limits to the current that Gdiff can deliver (Fig. 12), [20]. This produces that, under fast input violating the op-amp slew rate, Cp charges at a constant rate, emulating the real behavior of the op-amp.
The diodes and the sources named Vpos, and Vneg [19, 20] establish an output signal limiter that allows reproducing the saturation of the real op-amps. The output stage is composed of the output resistance Rout and a unity-gain buffer that avoids load effects in the internal nodes of the model. The source E2 compensates in the voltage limiter, the voltage drops in Rout.
1.2 Generation of the fault-free pattern from the experimental measurement. Source of variability: variations inter-chip.
In Sect. 4.2, the fault-free pattern was acquired from the measurements in one chip under temperature variations. Here we consider a different experiment with variations inter-chip for the second-order filter. The temperature is not modified, and slight variations around 20 °C are allowed.
The experimental setup was similar to the one shown in Fig. 3, without the air heater. Additionally, eight chips configured with the same filter were measured in the Psoc1 Eval board. The DTW threshold was obtained after the process described in Sect. 4.3. The Sett value was 3.5%, without window.
The fault simulation process included catastrophic faults in switches and deviation faults in capacitors of Sect. 5.1. The fault coverage was 100% for catastrophic faults. Table 11 shows the minimal deviations, positive and negative, that can be detected in capacitors. These values are higher than those reported when the source of variation is the temperature, but they are also lower than 5%, showing that the test strategy can be applied when the source of variation is inter-chip.
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Dri, E., Peretti, G. & Romero, E. Fault detection in configurable switched-capacitor filters using transient analysis and dynamic time warping. Analog Integr Circ Sig Process 108, 291–304 (2021). https://doi.org/10.1007/s10470-021-01888-x
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DOI: https://doi.org/10.1007/s10470-021-01888-x