Abstract
Hardware Trojans (HT) have emerged as a significant threat to both the IC industry and the military due to their stealthy nature and destructive capabilities. An HT is a small piece of hardware (circuit) embedded by an adversary to disrupt the victim circuit’s regular operation. As a result, it becomes an utmost necessity to distinguish standard signals from them. The detection of HT has become critical due to the presence of enormous search space combined with its small size. A clustering-based approach is proposed to identify benign signals in this work. The proposed approach combines both transition probability and combinational controllability to generate an effective HT free whitelist. It reduces the overhead of search space for HT detection. The clusters generated (whitelist) are analyzed in the presence of several ultra-small triggers which advocates the efficacy of the proposed solution. Simulation results on various ISCAS benchmark circuits validate the significance and quality of such clusters in terms of observed transition. Experimental results also underpin the proposed methodology’s superiority over existing techniques by identifying proper whitelist easily.
Similar content being viewed by others
Data Availability
The ISCAS benchmark circuits used (Bench format) in this experiment are open source and are freely available from http://www.pld.ttu.ee/~maksim/benchmarks/. Additionally, the trigger inserted data sets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.
References
Adee S (2008) The hunt for the kill switch. IEEE Spectr 45(5):34–39
Bazzazi A, Shalmani MTM, Hemmatyar AMA (2017) Hardware trojan detection based on logical testing. J Electron Test 33(4):381–395
Chakraborty RS, Pagliarini S, Mathew J, Rajendran SR, Devi MN (2017) A flexible online checking technique to enhance hardware trojan horse detectability by reliability analysis. IEEE Trans Emerg Top Comput 5(2):260–270
Chakraborty RS, Wolff F, Paul S, Papachristou C, Bhunia S (2009) Mero: A statistical approach for hardware trojan detection. In C. Clavier and K. Gaj, editors, Cryptographic Hardware and Embedded Systems - CHES 2009, pp 396–410 Springer Berlin Heidelberg
Dong C, He G, Liu X, Yang Y, Guo W (2019) A multi-layer hardware trojan protection framework for iot chips. IEEE Access 7:23628–23639
Dupuis S, Flottes M, Di Natale G, Rouzeyre B (2018) Protection against hardware trojans with logic testing: Proposed solutions and challenges ahead. IEEE Design Test 35(2):73–90
Francq J, Frick F (2015) Introduction to hardware trojan detection methods. In 2015 Design, Automation Test in Europe Conference Exhibition (DATE) pp. 770–775
Fyrbiak M, Wallat S, Swierczynski P, Hoffmann M, Hoppach S, Wilhelm M, Weidlich T, Tessier R, Paar C (2019) Hal-the missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion. IEEE Trans Dependable Secure Comput 16(3):498–510
Goldstein L (1979) Controllability/observability analysis of digital circuits. IEEE Transactions on Circuits and Systems 26(9):685–693
Govindan V, Chakraborty RS, Santikellur P, Chaudhary AK (2018) A hardware trojan attack on fpga-based cryptographic key generation: Impact and detection. Journal of Hardware and Systems Security 2(3):225–239
Hasegawa K, Oya M, Yanagisawa M, Togawa N (2016) Hardware trojans classification for gate-level netlists based on machine learning. In 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 203–206
Hasegawa K, Yanagisawa M, Togawa N (2018) A hardware-trojan classification method utilizing boundary net structures. In 2018 IEEE International Conference on Consumer Electronics (ICCE), pp 1–4
He Y, Huang K (2019) Trigger identification using difference-amplified controllability and dynamic transition probability for hardware trojan detection. IEEE Trans Inf Forensics Secur
Ismari D, Plusquellic J, Lamech C, Bhunia S, Saqib F (2016) On detecting delay anomalies introduced by hardware trojans. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 1–7
Karri R, Rajendran J, Rosenfeld K, Tehranipoor M (2010) Trustworthy hardware: Identifying and classifying hardware trojans. Computer 43(10):39–46
Lee H, Ha D (1993) Atalanta: An efficient atpg for combinational circuits. Technical Report, 93-12, Dept of Electrical Engineering, Virginia Polytechnic
Liu Y, He J, Ma H, Zhao Y (2019) Hardware trojan detection leveraging a novel golden layout model towards practical applications. J Electron Test 35(4):529–541
Macqueen J (1967) Some methods for classification and analysis of multivariate observations. In 5-th Berkeley Symposium on Mathematical Statistics and Probability, pp 281–297
Mahajan YS, Fu Z, Malik S (2004) An efficient sat solver. In International Conference on Theory and Applications of Satisfiability Testing, pp 360–375. Springer
Manivannan S, Kuppusamy L, Babu NSC (2020) Trap-gate: A probabilistic approach to enhance hardware trojan detection and its game theoretic analysis. J Electron Test 36(5):607–616
Mondal A, Mahalat MH, Mandal S, Roy S, Sen B (2019) A novel test vector generation method for hardware trojan detection. In 2019 32nd IEEE International System-on-Chip Conference (SOCC) (SOCC 2019), Singapore
Narasimhan S, Du D, Chakraborty RS, Paul S, Wolff FG, Papachristou CA, Roy K, Bhunia S (2013) Hardware trojan detection by multiple-parameter side-channel analysis. IEEE Trans Comput 62(11):2183–2195
Nigh C, Orailoglu A (2021) Adatrust: Combinational hardware trojan detection through adaptive test pattern construction. IEEE Trans Very Large Scale Integr VLSI Syst pp 1–14
Nourian M, Fazeli M, Hély D (2018) Hardware trojan detection using an advised genetic algorithm based logic testing. J Electron Test 34(4):461–470
Pan Z, Mishra P (2021) Automated test generation for hardware trojan detection using reinforcement learning. In Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASPDAC ’21, pp 408–413 Association for Computing Machinery, New York, NY, USA
Pedregosa F, Varoquaux G, Gramfort A, Michel V, Thirion B, Grisel O, Blondel M, Prettenhofer P, Weiss R, Dubourg V, Vanderplas J, Passos A, Cournapeau D, Brucher M, Perrot M, Duchesnay E (2011) Scikit-learn: Machine learning in Python. J Mach Learn Res 12:2825–2830
Saha S, Chakraborty RS, Nuthakki SS, Mukhopadhyay D (2015) Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability. In T. Güneysu and H. Handschuh, editors, Cryptographic Hardware and Embedded Systems – CHES 2015, pp 577–596 Springer Berlin Heidelberg
Salmani H (2017) Cotd: Reference-free hardware trojan detection and recovery based on controllability and observability in gate-level netlist. IEEE Trans Inf Forensics Secur 12(2):338–350
Salmani H, Tehranipoor M, Plusquellic J (2012) A novel technique for improving hardware trojan detection and reducing trojan activation time. IEEE Trans. Very Large Scale Integr VLSI Syst 20(1):112–125
Sebt SM, Patooghy A, Beitollahi H, Kinsy M (2018) Circuit enclaves susceptible to hardware trojans insertion at gate-level designs. IET Comput Digit Tech 12(6):251–257
Shabani A, Alizadeh B (2020) Pmtp: A max-sat-based approach to detect hardware trojan using propagation of maximum transition probability. IEEE Trans Comput Aided Des Integr Circuits Syst 39(1):25–33
Shakya B, He T, Salmani H, Forte D, Bhunia S, Tehranipoor M (2017) Benchmarking of hardware trojans and maliciously affected circuits. Journal of Hardware and Systems Security 1(1):85–102
Testability Measurement Tool, Version 2.2.5298.15733 [online]. Available: https://sourceforge.net/projects/testabilitymeasurementtool/
Venugopalan V, Patterson CD (2018) Surveying the hardware trojan threat landscape for the internet-of-things. Journal of Hardware and Systems Security 2(2):131–141
Wolff F, Papachristou C, Bhunia S, Chakraborty RS (2008) Towards trojan-free trusted ics: Problem analysis and detection scheme. In 2008 Design, Automation and Test in Europe, pp 1362–1365
Xiao K, Forte D, Jin Y, Karri R, Bhunia S, Tehranipoor M (2016) Hardware trojans: Lessons learned after one decade of research. ACM Trans Des Autom Electron Syst 22:1–23
Zhou B, Zhang W, Thambipillai S, Teo JKJ (2014) A low cost acceleration method for hardware trojan detection based on fan-out cone analysis. In 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp 1–10
Zhou B, Zhang W, Thambipillai S, Jin JT, Chaturvedi V, Luo T (2016) Cost-efficient acceleration of hardware trojan detection through fan-out cone analysis and weighted random pattern technique. IEEE Trans Comput Aided Des Integr Circuits Syst 35(5):792–805
Acknowledgment
This work is supported by DST-SERB under core research scheme (Formerly EMR) through grant # EMR/2017/003206 and Young Faculty Research Fellow of Visvesvaraya PhD scheme # [MLA/MUM/GA/10(37)B].
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: C. A. Papachristou
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Mondal, A., Biswal, R.K., Mahalat, M.H. et al. Hardware Trojan Free Netlist Identification: A Clustering Approach. J Electron Test 37, 317–328 (2021). https://doi.org/10.1007/s10836-021-05953-1
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-021-05953-1