Abstract
True Random Number Generators (TRNGs) are indispensable in modern cryptosystems. Unfortunately, to guarantee high entropy of the generated numbers, many TRNG designs require a complex implementation procedure, often involving manual placement and routing. In this work, we introduce, analyse, and compare three dynamic calibration mechanisms for the COherent Sampling ring Oscillator based TRNG: GateVar, WireVar, and LUTVar, enabling easy integration of the entropy source into complex systems. The TRNG setup procedure automatically selects a configuration that guarantees the security requirements. In the experiments, we show that two out of the three proposed mechanisms are capable of assuring correct TRNG operation even when an automatic placement is carried out and when the design is ported to another Field-Programmable Gate Array (FPGA) family. We generated random bits on both a Xilinx Spartan 7 and a Microsemi SmartFusion2 implementation that, without post processing, passed the AIS-31 statistical tests at a throughput of 4.65 Mbit/s and 1.47 Mbit/s, respectively.
- Josep Balasch, Florent Bernard, Viktor Fischer, Miloš Grujić, Marek Laban, Oto Petura, Vladimir Rožić, Gerard van Battum, Ingrid Verbauwhede, Marnix Wakker, and Bohan Yang. 2018. Design and testing methodologies for true random number generators towards industry certification. In Proceedings of the 2018 IEEE 23rd European Test Symposium (ETS’18), Vol. 2018. IEEE, 1–10. Google ScholarCross Ref
- Mathieu Baudet, David Lubicz, Julien Micolod, and André Tassiaux. 2011. On the security of oscillator-based random number generators. J. Cryptol. 24, 2 (2011), 398–425. Google ScholarDigital Library
- Florent Bernard, Viktor Fischer, and Boyan Valtchanov. 2010. Mathematical model of physical RNGs based on coherent sampling. Tatra Mount. Math. Publ. 45, 1 (2010), 1–14.Google ScholarCross Ref
- Abdelkarim Cherkaoui, Viktor Fischer, Laurent Fesquet, and Alain Aubert. 2013. A very high speed true random number generator with entropy assessment. In Proceedings of the 15th International Workshop on Cryptographic Hardware and Embedded Systems (CHES’13). Springer, Grenoble, France, 179–196. Google ScholarDigital Library
- Jean Luc Danger, Sylvain Guilley, and Philippe Hoogvorst. 2009. High speed true random number generator based on open loop structures in FPGAs. Microelectr. J. 40, 11 (2009), 1650–1656. Google ScholarDigital Library
- Lawrence E. Bassham III, Andrew L. Rukhin, Juan Soto, James R. Nechvatal, Miles E. Smid, Elaine B. Barker, Stefan D. Leigh, Mark Levenson, Mark Vangel, David L Banks, et al. 2010. A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications. Technical Report. NIST, Gaithersburg, MD. Google ScholarDigital Library
- Wolfgang Killmann and Werner Schindler. 2011. A proposal for: Functionality classes for random number generators. Retrieved May 22, 2019 from https://cosec.bit.uni-bonn.de/fileadmin/user_upload/teaching/15ss/15ss-taoc/01_AIS31_Functionality_classes_for_random_number_generators.pdf. Google Scholar
- Paul Kohlbrenner and Kris Gaj. 2004. An embedded true random number generator for FPGAs. In Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field-Programmable Gate Arrays. ACM, 71–78. Google ScholarDigital Library
- L. H. A. Leunissen, W. Zhang, W. Wu, and S. H. Brongersma. 2006. Impact of line edge roughness on copper interconnects. J. Vacuum Sci. Technol. B 24, 4 (2006), 1859–1862.Google ScholarCross Ref
- Yuan Ma, Jingqiang Lin, Tianyu Chen, Changwei Xu, Zongbin Liu, and Jiwu Jing. 2014. Entropy evaluation for oscillator-based true random number generators. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 544–561. Google ScholarDigital Library
- Abhranil Maiti and Patrick Schaumont. 2009. Improving the quality of a physical unclonable function using configurable ring oscillators. In Proceedings of the 2009 International Conference on Field Programmable Logic and Applications. IEEE, 703–707.Google ScholarCross Ref
- Mehrdad Majzoobi, Farinaz Koushanfar, and Srinivas Devadas. 2011. FPGA-based true random number generation using circuit metastability with adaptive feedback control. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 17–32. Google ScholarDigital Library
- Anindo Mukherjee and Kevin Skadron. 2006. Measuring Parameter Variation on an FPGA using Ring Oscillators. Univ. of Virginia Dept. of Computer Science Tech Report CS-2006-16. University of Virginia, Dept. of Computer Science, Charlottesville, VA.Google Scholar
- NIST. 2001. Security Requirements for Cryptographic Modules. Technical Report. NIST, Washington, DC.Google Scholar
- Adriaan Peetermans, Vladimir Rožić, and Ingrid Verbauwhede. 2019. A highly-portable true random number generator based on coherent sampling. In Proceedings of the 2019 29th International Conference on Field Programmable Logic and Applications (FPL’19). IEEE, 218–224.Google ScholarCross Ref
- Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, and Lilian Bossuet. 2016. A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. In Proceedings of the 2016 26th International Conference on Field-Programmable Logic and Applications (FPL’16). IEEE, 1–10.Google ScholarCross Ref
- Tao Pi and Patrick J. Crotty. 2003. FPGA lookup table with transmission gate structure for reliable low-voltage operation. US Patent 6,667,635.Google Scholar
- Vladimir Rožić, Bohan Yang, Wim Dehaene, and Ingrid Verbauwhede. 2015. Highly efficient entropy extraction for true random number generators on FPGAs. In Proceedings of the 52nd Annual Design Automation Conference. IEEE, 116:1–116:6. Google ScholarDigital Library
- Willy Sansen. 2007. Analog Design Essentials. Vol. 859. Springer Science & Business Media.Google Scholar
- Meltem Sönmez Turan, Elaine Barker, John Kelsey, Kerry A. McKay, Mary L. Baish, and Mike Boyle. 2018. Recommendation for the Entropy Sources used for Random Bit Generation. Technical Report. NIST, Gaithersburg, MD.Google Scholar
- Boyan Valtchanov, Viktor Fischer, and Alain Aubert. 2009. Enhanced TRNG based on the coherent sampling. In Proceedings of the 2009 3rd International Conference on Signals, Circuits and Systems (SCS’09). IEEE, 1–6.Google ScholarCross Ref
- Michal Varchola and Miloš Drutarovskỳ. 2010. New high entropy element for FPGA based true random number generators. In Proceedings of the International Workshop on Cryptographic Hardware and Embedded Systems. Springer, 351–365. Google ScholarDigital Library
- Janet Wang, Praveen Ghanta, and Sarma Vrudhula. 2004. Stochastic analysis of interconnect performance in the presence of process variations. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD’04). IEEE, 880–886. Google ScholarDigital Library
- Piotr Zbigniew Wieczorek and Krzysztof Golofit. 2014. Dual-metastability time-competitive true random number generator. IEEE Trans. Circ. Syst. I: Regul. Pap. 61, 1 (2014), 134–145.Google ScholarCross Ref
- Xilinx. 2018. Vivado Design Suite User Guide: Implementation (UG904). Retrieved July 2, 2020 from https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug904-vivado-implementation.pdf.Google Scholar
- Bohan Yang, Vladimir Rožić, Miloš Grujić, Nele Mentens, and Ingrid Verbauwhede. 2018. ES-TRNG: A high-throughput, low-area true random number generator based on edge sampling. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018, 3 (2018), 267–292.Google ScholarCross Ref
- Jing Yang, Yuan Ma, Tianyu Chen, Jingqiang Lin, and Jiwu Jing. 2016. Extracting more entropy for TRNGs based on coherent sampling. In Proceedings of the International Conference on Security and Privacy in Communication Systems. Springer, 694–709.Google Scholar
Index Terms
- Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling
Recommendations
An embedded true random number generator for FPGAs
FPGA '04: Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arraysField Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper ...
FPGA Design of an Open-Loop True Random Number Generator
DSD '13: Proceedings of the 2013 Euromicro Conference on Digital System DesignThis paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since ...
Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration
DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and ToolsThis paper presents the hardware implementation of the widely known NIST Statistical Test Suite – a battery of statistical tests for pseudorandom number generators (PRNGs) and true random number generators (TRNGs) – in a single Xilinx FPGA chip, using ...
Comments