Mitigating the processor aging through dynamic concurrency throttling

Highlights

• Presents the need for a DCT tool that specifically optimizes the processor aging.

• Hebe: a transparent aging-aware thread throttling approach for OpenMP applications.

• It learns, at run-time, the ideal degree of TLP for each parallel region.

• Hebe outperforms state-of-the-art approaches.

• Very close results from the best solution given by an exhaustive search.

Abstract

The increase in the number of cores in a single chip brings better capabilities to exploit thread-level parallelism (TLP). However, since power dissipated per area rises at each new node generation, higher temperatures are achieved, speeding up the aging of hardware components, which may provoke undesired system behavior. Considering that many applications do not scale with the number of cores, their execution with the maximum TLP available will not only degrade performance, but also unnecessarily increase temperature, further accelerating aging. Given that, we propose Hebe, a dynamic concurrency throttling approach that learns at run-time the degree of TLP that reduces the aging for OpenMP applications. Hebe is totally transparent, needing no modifications in the original binary code. With a set of extensive experiments (fifteen benchmarks and four multicore platforms), we show that Hebe outperforms state-of-the-art approaches with very close results from the best possible solution given by an exhaustive search.

Introduction

To satisfy the demand for performance of applications from many domains in big data centers and cloud-based systems, the number of cores in a single chip package has been growing at the same pace as the increasing transistor density. However, considering that power dissipated per area rises at each new node generation (i.e., the well-known end of Dennard Scaling), heat dissipation has become a significant issue when exploiting thread-level parallelism (TLP). Besides the common problems, like cooling, the increase of heat dissipation raises the operating temperature, which influences some of the main causes of aging of hardware components (e.g., negative bias temperature instability - NBTI), shortening their lifetime.

NBTI consists of a vital reliability problem in metal-oxide-silicon (MOS) devices. It refers to the generation of positive oxide charge and interface traps in MOS structures under a combination of elevated temperatures and negative gate voltages [62], [11]. This, in turn, increases the threshold voltage ($V_{th}$), which will have adverse effects on current and propagation delay, degrading the device performance [57]. The impact of NBTI on the processor aging has become more significant in modern devices due to the aggressive down-scaling of device geometry and compact device integration. Both strongly affect the operating temperature, intensifying the processor aging [25]. In the end, this increase in the threshold voltage may provoke undesired system behavior (e.g., electromigration, dielectric breakdown, and stress migration [19]) for many critical applications, further increasing the operating expenses. Therefore, controlling the operating temperature is essential to avoid shortening the hardware lifespan.

Given that, when running a parallel application, the processor temperature rises as the number of threads increases, mainly as a result of the increase in power dissipation due to the switching activity in the hardware components (cores and caches). This behavior can be observed in Fig. 1a for the execution of BT kernel from the NAS Parallel Benchmark [5] on an Intel Xeon 32-core machine (retired from our experiments, discussed in Section 3). It shows the average CPU power and temperature for the application execution with a different number of threads (from 2 to 32). As one can observe by comparing Fig. 1a and Fig. 1b, the average NBTI per second of execution (raw numbers got from Eq. (1)) proportionally grows with the temperature rise. Therefore, there is a trade-off between temperature rise, the benefits it brings to lower the total execution time, and the impact they have on aging due to the NBTI [43], [44]. In the end, they are all directly related to how many threads are distributed across the cores in a parallel application.

Nevertheless, many applications do not scale as the number of threads increases due to several hardware related reasons: Instruction issue width saturation, off-chip bus saturation, data synchronization, and concurrent shared memory accesses [65], [64], [52], [39]. It means that in many cases, executing a given application in the regular way (i.e., splitting the application into as many threads as possible to use all the available cores) will result in non-optimal use of the available resources, not delivering the best trade-off between performance and temperature and accelerating the impact of NBTI on the aging process. Therefore, by artificially decreasing the number of threads (i.e., thread throttling) for some parallel regions, one can rightly tune the parameters mentioned above to achieve the best performance/temperature ratio and reduce the impact of NBTI on the processor aging. We show that it is possible in Fig. 2 for the execution of Streamcluster application from the Rodinia benchmark suite [17]: the lowest value of NBTI (Fig. 2b) is achieved when running the application with eight threads, which has the best trade-off between performance and temperature (Fig. 2a). Hence, by executing this application with the ideal degree of TLP (e.g., eight threads) instead of with the maximum number of threads (which would be the default behavior), the impact of NBTI on the processor aging is 24% lower.

Given the scenario above, we propose Hebe, a transparent aging-aware thread throttling approach for OpenMP Applications. By using an efficient search algorithm, it automatically learns, at run-time, the ideal number of threads for each parallel region aiming to reduce the impact of NBTI on the processor aging. This dynamic capability to adapt is key, since thread balancing will vary depending on intrinsic characteristics of the parallel application at hand (e.g., input set and number of parallel regions), as well as the microarchitecture on which it will execute (e.g., number of cores and instruction-set architecture). Hebe improves previous work [43] by considering the optimization of a more realistic phenomena on the processor aging (i.e. it uses NBTI as the main metric).

We validate Hebe through the execution of fifteen well-known benchmarks on four distinct multicore platforms (AMD and Intel) We compare Hebe to different scenarios: i) the standard way that parallel applications are executed (STD), that is, with the maximum possible number of threads available; ii) a built in feature of OpenMP that dynamically changes the number of threads (OMP_Dynamic); iii) a thermal-aware adaptive energy minimization approach for OpenMP applications proposed by Shafik et al. [60] (TA-OMP). We show that, by using Hebe, the impact of NBTI on the processor aging is up to 80% lower than the one presented by the STD configuration; 87% lower than the OMP_Dynamic; and 91% lower than the TA-OMP approach.

In order to reinforce the need for a tool that specifically optimizes the impact of NBTI on the processor aging, we also compare the results of Hebe when the objective function is changed to optimize performance, energy, or EDP instead of aging. Fig. 3 presents the NBTI of each configuration normalized to Hebe w.r.t. the geometric mean of the entire benchmark set on each multicore processor. With that, we show that the performance, energy, and EDP oriented setup present an NBTI 12%, 12%, and 10% higher than the original objective function, respectively. We also compare Hebe to two well-known approaches that target performance and energy rather than aging: the FDT [65] and the Varuna programming model [61]. Finally, to measure the cost of the learning curve for converging to the ideal number of threads brought by its dynamic adaptation, we also compare Hebe to the solution provided by an exhaustive search. It executes each parallel region with its predefined ideal number of threads, without the learning overheads. From this, we found that the average cost of Hebe to reduce the impact of NBTI on the processor aging is less than 1.0% for most of the benchmarks.

The remainder of the manuscript is organized as follows. Hebe is described in Section 2. The benchmarks and execution environment used to validate Hebe are described in Section 3. We discuss the results in Section 4. We describe the related work and compare it to Hebe in Section 5, while the final considerations are drawn in Section 6.