Investigations of short-circuit failure in double trench SiC MOSFETs through three-dimensional electro-thermal-mechanical stress analysis

https://doi.org/10.1016/j.microrel.2021.114163Get rights and content

Highlights

  • In this study, the short-circuit failure mechanisms of 1.2 kV double trench SiC MOSFETs at 400 V and 800 V drain-source bias are investigated by experiments and three-dimensional numerical TCAD simulations.

  • The fracture of the gate interlayer dielectric was directly detected by using the FIB-SEM analysis.

  • The thermal runaway failure was confirmed as the 800 V shortcircuit failure mode.

  • The simulation results of 400 V short-circuit showed that the high-level mechanical stress concentrated at the gate interlayer dielectric during the short-circuit time was the cause of the formation of the conductive paths.

  • The simulation results of 800 V shortcircuit showed that the activation of bipolar junction transistor initially occurred near the gate cross-corner, and then spread throughout the entire cell.

Abstract

In this study, the short-circuit failure mechanisms of 1.2 kV double trench SiC MOSFETs were investigated by experiment and three-dimensional numerical TCAD simulation. Damage at the gate interlayer dielectric was confirmed as the cause of failure in the case of 400 V drain-source bias short-circuit transient. The three-dimensional TCAD simulation results showed that the high level of mechanical stress could cause the structural damage observed in the interlayer dielectric. Stress component analysis showed that tensile stress and shear stress were the principal stresses that caused the damage. The typical thermal runaway failure caused by activation of bipolar characteristics at extremely high temperature was confirmed, by experiment and simulation, in the case of the 800 V drain-source bias short-circuit transient. The three-dimensional simulation results indicated that activation of the bipolar junction transistor initially occurred near the gate cross-corner, and then spread throughout the entire cell.

Introduction

Owing to their excellent electrical and thermal properties, silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs) have been widely utilized in power electronic systems to replace their silicon counterparts. SiC MOSFET features such as rapid switching speed, high block voltage, low conductive resistance, and high thermal conductivity can significantly reduce the power loss and systems volume. Therefore, the performance of power systems can be greatly improved through the utilization of SiC MOSFETs [1].

Applications such as electric vehicle motors and power transformation systems require long-term trouble-free operation. As a consequence, stringent requirements are proposed with regard to SiC MOSFETs' reliability. Among the many fault mechanisms, the short-circuit event is one of the harsh operating modes that can cause the permanent failure of switching devices. SiC MOSFETs must endure high electro-thermal stress during a short-circuit transient, without failure, before the activation of the protection circuit. Various studies have reported on the short-circuit characteristics of SiC MOSFETs. Most have focused on electrical failure and degradation [[2], [3], [4], [5], [6], [7], [8]]. Recently, gate shorting failure due to mechanical stress has been investigated. [9] investigated SiO2 dielectric degradation in planar SiC MOSFETs after a short-circuit transient, under varying temperature, drain-source voltage, and gate-source bias; and revealed that structural damage at the gate interlayer dielectric caused an increase in the gate-leakage and drain-leakage current. In [[10], [11], [12], [13]], the short-circuit failure modes at different drain-source voltages, as well as the corresponding electro-thermal analytical models, were summarized. It was found that at low or medium drain-source voltage, gate shorting after the short-circuit transient is a common failure mode. In [14,15], mechanical stress analysis was performed for gate shorting failure in planar and asymmetric trench SiC MOSFETs after a short-circuit transient. The results indicated that the cause of failure was the filling of cracks with melted source aluminum, due to the high mechanical stress at the gate interlayer dielectric. Gate shorting failure also occurred in double trench SiC MOSFETs after a short-circuit transient [16].

In the aforementioned mechanical stress analysis cases [14,15], the planar and asymmetric trench SiC MOSFETs had a stripe cell design, which enables three-dimensional stress to be simplified to two-dimensional stress in simulations. In contrast, the present study investigated the mechanical stress failure in double trench SiC MOSFETs, and since these have a square unit cell design, three-dimensional electro-thermal-mechanical simulation was here performed, for the first time, to investigate short-circuit failure in SiC MOSFETs. A wide range of visualized three-dimensional mechanical stress analysis, as well as failure current analysis of the thermal runaway conditions, are presented.

Section snippets

Short-circuit characteristics at 400 V DC bias

The device under test (DUT) was a double trench SiC power MOSFET (SCT3030AL; rated current, 70 A). The breakdown voltage of the DUT was 1300 V, with a drain current (Id) of 1 mA, and can be used as 1.2 kV class MOSFET. The specific on-resistance (Ron·A) was 2.8 mΩ·cm2 at Vgs of 20 V. The gate threshold voltage was 4.1 V at Vds of 10 V and Id of 1 mA. The active area of the DUT was roughly 9.2 mm2.

Fig. 1 shows the test equipment setup and a schematic of the equivalent circuit. The short-circuit

Post-failure chips examination

In order to further investigate the short-circuit failure mechanisms, the post-failure MOSFETs were decapped by chemical etching. Fig. 4(a) and (b) respectively show the surface of the chips after the 400 V and 800 V short-circuit tests. No obvious damage can be observed on the chip surface after the 400 V short-circuit test (Fig. 4(a)); however, after the 800 V short-circuit transient, burn-out marks are observable on the source pad near the bonding wire (Fig. 4(b)). These marks indicate

Electro-thermal-mechanical TCAD simulation

Sentaurus TCAD simulation with coupled electro-thermal conditions is used to investigate the short-circuit failure mechanism [17]. As aforementioned, the double trench SiC MOSFET has a square unit (vs. stripe) cell design; thus, simplifying the volume stress to 2D plane stress may not reflect the mechanical stress distribution accurately. Therefore, in the present study, a 3D device structure was used in the TCAD (Fig. 7). The thickness and doping concentration of the drift region were set at

Conclusion

In this study, the short-circuit failure mechanisms of double trench SiC MOSFETs were investigated, at 400 V and 800 V drain-source DC bias, by experiment and three-dimensional numerical TCAD simulation. Gate to source shorting caused by damage to the gate interlayer dielectric was the reason for the 400 V short-circuit failure, with FIB-SEM analysis revealing conductive paths between the gate poly-Si and the source aluminum. The three-dimensional electro-thermal-mechanical simulation showed

CRediT authorship contribution statement

Kailun Yao: Methodology, Software, Simulation, Writing- Original draft preparation.

Hiroshi Yano: Supervision.

Noriyuki Iwamuro: Supervision.

Acknowledgement

The authors would like to express special thanks to Dr. Y. Yamashita of Toyota Central R&D Laboratories Inc., and the technical support staff of Sentaurus Device and Sentaurus Interconnect from Synopsys Inc., for their support in this study.

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