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An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process

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Abstract

This paper presents the design and simulation of a modified CMOS low noise amplifier (LNA) circuit in 180 nm CMOS standard technology. We modified a cascade LNA using π model of capacitor circuit. Impedance matching network at the input of proposed circuit provides low noise figure (NF) and suitable gain at the operating frequency of 6 GHz. Obtained simulation results after extracting post layout (with total chip size 2500*1600 μm2) provide higher gain (S21) of 19.75 dB and noise figure of 1.14 dB. The reverse isolation (S12) of the LNA is also achieved to − 30.8 dB. A comparison table confirms that the proposed LNA circuit has better performance than the other recent works.

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Acknowledgements

The authors would like to thank A. Nabavi, A. Khoei, and Kh. Hadidi.

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  1. Department of Electrical Electronics Engineering, Mahabad Branch, Islamic Azad University, 5913933137, Mahabad, Iran

    Farshad Azizi & Ghader Yosefi

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  1. Farshad Azizi
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  2. Ghader Yosefi
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Correspondence to Ghader Yosefi.

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Azizi, F., Yosefi, G. An Enhanced Low Noise Amplifier Circuit at 6 GHz Center Frequency and NF Improvement in 180 nm CMOS Process. Wireless Pers Commun 120, 2907–2917 (2021). https://doi.org/10.1007/s11277-021-08591-0

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  • DOI: https://doi.org/10.1007/s11277-021-08591-0

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