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An FPGA-Based Performance Evaluation of Artificial Neural Network Architecture Algorithm for IoT

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Abstract

Nowadays, the high number of devices and applications connected to the Internet has generated a great amount of data being which makes privacy and protection a more challenging task. In addition, new technologies, such as the Internet of Things, incorporate many resource-constrained devices in the network. Reliable cryptography algorithms have to be employed to deal with this problem, which also needs to be efficiently implemented in small devices. There are several algorithms for this purpose, among them, neural cryptography. In this context, this work proposes the implementation of an artificial neural network architecture called tree parity machine (TPM) to perform the exchange of keys through the mutual learning of these networks. This method is not based on number theory, which makes it less computationally costly, and can be an alternative for embedded systems, which generally have several limitations in the processing capacity and resources used. In the area of embedded systems, FPGAs have gained more space, thanks to their reconfiguration capacity. Thus, different methods for implementing a TPM in FPGA were tested and analyzed, in order to optimize the following performance parameters, the response time, the maximum frequency of operation, and the consumed area of the FPGA considering logical elements, embedded multipliers, and registers. In addition, software implementation based on a multi-core CPU was used for comparison purposes. Experimental results demonstrated that the implementation of parallelism in FPGA for different blocks of the TPM weight matrix reached the best performance results. Thus, our proposal intends to develop an economic component in terms of resource consumption, however, maintaining the characteristic of high processing capacity. Therefore, the methodologies presented in this paper intends to be a useful reference to optimize future implementations in FPGA for cryptography applications.

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Acknowledgements

This work was supported in part by Minas Gerais State Research Support Foundation (FAPEMIG) under Grant 11230 and Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq).

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Authors and Affiliations

  1. Department of Computer Science, Federal University of Lavras, Lavras, 37200-900, Brazil

    Arthur A. M. Teodoro, Bruno A. Silva, Renata L. Rosa & Demóstenes Z. Rodríguez

  2. Institute of Systems Engineering and Information Technology (IESTI), Federal University of Itajubá, Itajubá, 37500-903, Brazil

    Otávio S. M. Gomes

  3. Department of Electrical Engineering, University of Central Punjab, Lahore, 54000, Pakistan

    Muhammad Saadi

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  1. Arthur A. M. Teodoro
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Teodoro, A.A.M., Gomes, O.S.M., Saadi, M. et al. An FPGA-Based Performance Evaluation of Artificial Neural Network Architecture Algorithm for IoT. Wireless Pers Commun 127, 1085–1116 (2022). https://doi.org/10.1007/s11277-021-08566-1

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