Research paper
Superconducting V3Si for quantum circuit applications

https://doi.org/10.1016/j.mee.2021.111570Get rights and content

Highlights

  • The development of CMOS-compatible superconducting materials enables the scaling of quantum technologies.

  • Superconducting silicides are ideal for integration, and V3Si is especially promising for its high critical temperature.

  • A process window is found within which V3Si can be crystallized, while preventing its complete consumption by VSi2 formation.

  • Earlier results indicated a negative impact of stress on the superconductivity of V3Si thin films (DOI: https://doi.org/10.1063/5.0038638).

  • This study finds that stresses in V3Si thin films can be controlled with the annealing temperature.

Abstract

V3Si thin films are known to be superconducting with transition temperatures up to 15 K, depending on the annealing temperature and the properties of the substrate underneath. Here we investigate the film structural properties with the prospect of further integration in silicon technology for quantum circuits. Two challenges have been identified: (i) the large difference in thermal expansion coefficient between V3Si and the Si substrate leads to large thermal strains after thermal processing, and (ii) the undesired silicide phase VSi2 forms when V3Si is deposited on silicon. The first of these is studied by depositing layers of 200 nm V3Si on wafers of sapphire and oxidized silicon, neither of which react with the silicide. These samples are then heated and cooled between room temperature and 860 °C, during which in-situ XRD measurements are performed. Analysis reveals a highly non-linear stress development during heating with contributions from crystallization and subsequent grain growth, as well as the thermal expansion mismatch between silicide and substrate, while the film behaves thermoelastically during cooling. The second challenge is explored by depositing films of 20, 50, 100 and 200 nm of V3Si on bulk silicon. For each thickness, six samples are prepared, which are then annealed at temperatures between 500 and 750 °C, followed by measurements of their resistivity, residual resistance ratio and superconducting critical temperature. A process window is identified for silicide thicknesses of at least 100 nm, within which a trade-off needs to be made between the quality of the V3Si film and its consumption by the formation of VSi2.

Introduction

Quantum technologies based on solid state matter are now spreading from academic laboratories to the most advanced semiconductor foundries [1,2]. Among the materials to be integrated, superconducting thin films are of major interest as they are part of many quantum architectures. For instance, such films can be used to manipulate, read and couple superconducting or spin qubits with the use of superconducting resonators [3,4], are developed for non-dissipative interconnections or can even be part of the quantum device itself when integrated as source and drain contacts of CMOS transistors. Since silicon technology is by far the most advanced method of nanofabrication, it is important to identify superconducting materials that are fully compatible with such an environment. Among these, silicides appear as the most suitable materials [5,6], and as V3Si has the highest known critical temperature of any silicide known so far [7,8], it is a prime candidate for these applications. Room-temperature resistivities down to ρ = 77 μΩcm have been obtained by the fabrication techniques discussed in this study (ρ = 70–77 μΩcm for single crystals [[9], [10], [11]]), and other methods to form thin films have obtained critical fields of Hc2 = 20 [12]. While contact resistances have not yet been extracted, the Schottky barrier height to phosphorus-doped (n) Si is known to be 0.16 V [13]. The material properties improve with increased annealing temperatures [14], and critical temperatures of 8 K can already be reached after annealing at 500 °C for 5 min. In working towards integration of V3Si, two key problems have been identified: (i) a reduction in the superconducting critical temperature due to increased thermal strain after annealing [14], and (ii) the formation of the non-superconducting phase VSi2 at the interface with a silicon channel or substrate.

In systems where reservoirs of both Si and V are available, the undesired phase VSi2 is expected to form, which is both the first phase to nucleate [15] and is thermodynamically favored [16]. This rules out the self-aligned silicide (SALICIDE) process for the formation of the desired V3Si, in which pure metal is deposited on exposed silicon contacts. Instead, it has motivated the adoption of V3Si sputtering from compound targets [17,18], after which an annealing step is required to trigger the crystallization. This thermal processing leads to the build-up of strain in the final silicide film, which is known to negatively affect its critical temperature [[19], [20], [21], [22], [23], [24]]. Earlier work has shown that this strain depends strongly on the mismatch in thermal expansion coefficient (TEC) between the silicide and the substrate, and can lead to a suppression in superconducting critical temperature Tc by 2 K on silicon [14]. Section II provides a detailed analysis of the impact of crystallization, grain growth and thermal expansion mismatch on the strongly temperature-dependent development of stress in V3Si thin films.

Besides causing the buildup of large tensile stresses, thermal processing of V3Si on silicon substrates also leads to the formation of VSi2. The presence of VSi2 at the interface between the superconducting V3Si and the Si substrate may not be a problem per se. It is imperative, however, that a layer of V3Si with a thickness on the order of its superconducting coherence length remains. The simultaneous formation of the two silicide phases after the deposition of amorphous V3Si on bulk silicon wafers is discussed in section III. We find that when 50 nm or less of V3Si is deposited, no superconductivity is observed after crystallization annealing. For layers of 100 or 200 nm, the superconducting critical temperature of the film is found to initially improve with annealing temperature, until at some point superconductivity disappears when all V3Si is consumed by a growing layer of VSi2.

Section snippets

In-situ XRD analysis

Sputtering a V3Si target leads to the deposition of an amorphous layer of the desired intermetallic compound which presents superconductivity at temperatures of around 1 K, far below that of the crystalline form (measured but not shown). In order to nucleate the crystalline V3Si phase, heat has to be applied. During the experiment described in the present section, the V3Si was isolated from any potential element (V and Si especially) that would affect the crystallization phenomenon. Thus,

Competition between V3Si and VSi2 formation

A second set of experiments was performed to study the stability of the superconducting V3Si phase on a silicon substrate. After sputter deposition of V3Si on a silicon substrate, an intermixing layer of Si and V can be expected to form where the atomic fraction of vanadium ranges from zero in the substrate to 3/4 within the deposited layer. Above this mixed zone, the precise matching of the deposited atomic ratio to the stoichiometry of V3Si will prevent the formation of VSi2. Within the mixed

Discussion

Instead of forming vanadium silicide by reactive diffusion, V3Si was directly sputtered from a compound target at the right stoichiometry, giving the advantages of having a sharp interface between the deposited layer and the substrate, and requiring no solid-state reaction to reach the desired phase. However, the interface must be better controlled in terms of impurities, and the V3Si is amorphous after deposition. First, the crystallization was studied on 2 types of substrate, oxidized silicon

Conclusion

Superconducting thin films are of increasing interest as solid-state quantum technologies are scaled up. To facilitate large-scale fabrication, as well as co-integration with classical electronics, it is important that the choice of superconducting material is compatible with CMOS technology. This report addresses two challenges for the integration of V3Si, which as a silicide with a superconducting critical temperature of up to 17 K [7,8] is a natural candidate in this context.

The first is the

Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

Declaration of Competing Interest

The authors declare no competing interests.

Acknowledgments

T.D.V. acknowledges the European Union's Horizon 2020 research and innovation programme under the Marie Skłodowska-Curie grant agreement No 754303. This work was supported by the French ANR project SUNISIDEUP (ANR-19-CE47-0010). JX Nippon are gratefully acknowledged for providing the V3Si deposition target. Part of this work, carried out on the Platform for Nanocharacterisation (PFNC), was supported by the “Recherche Technologique de Base” program of the French National Research Agency (ANR).

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