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A 2\(^7\)-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS

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Abstract

In this work, we propose a 2\(^7\)-1, 20-Gb/s, low-power, charge-steering, half-rate pseudorandom bit sequence (PRBS) generator in 1.2 V, 65 nm CMOS. At the target data rate, the proposed charge-steering implementation has the lowest power consumption of 0.2 mW/Gb/s compared to the current-mode PRBS generator implementations, thanks to the discrete nature of the charge-steering latch circuit topology, which consumes a power of 22.3 \(\upmu \)W/Gb/s, whereas the CML latch consumes 60 \(\upmu \)W/Gb/s. The post-layout performance of the implementation shows a differential output voltage swing of 1.5 V, timing jitter of 5 ps and figure of merit of 0.038-pJ/bit at 20-Gb/s and it occupies an area of 0.026 \(\hbox {mm}^2\). Thus, the proposed power efficient charge-steering half-rate PRBS generator implementation is an attractive candidate for on-chip bit-error-rate test and measurement applications.

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Data Availability Statement

Data sharing not applicable to this article as no datasets were generated or analysed during the current study.

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Authors and Affiliations

  1. CASEST-Centre for Advanced Studies in Elecronics Science and Technology, Univesity of Hyderabad, Hyderabad, India

    Prema Kumar Govindaswamy

  2. School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, Odisha, India

    Vijaya Sankara Rao Pasupureddi

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  1. Prema Kumar Govindaswamy
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  2. Vijaya Sankara Rao Pasupureddi
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Govindaswamy, P.K., Pasupureddi, V.S.R. A 2\(^7\)-1, 20-Gb/s, Low-Power, Charge-Steering Half-Rate PRBS Generator in 1.2 V, 65 nm CMOS. Circuits Syst Signal Process 40, 5553–5571 (2021). https://doi.org/10.1007/s00034-021-01732-7

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