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A Novel High-Performance Hybrid Full Adder for VLSI Circuits

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Abstract

This article presents a high-performance hybrid full adder (HPHFA) designed with static CMOS logic and pass transistor logic to achieve better power delay product (PDP). The circuit was implemented using cadence virtuoso tool on gpdk 90 nm and 45 nm CMOS process technologies. Further, the structure has been extended to 32 bits to test the performance of HPHFA in higher-order circuitry. The proposed design was compared with popular conventional adders based on power consumption, delay and PDP. The proposed adder cell achieves 5.08–70.50% and 6.31–48.03% improvement in speed and power consumption, respectively, in 45 nm when compared to other conventional full adders (FAs). Also, the proposed design exhibits robustness against process variation and noise immunity with better driving capability.

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Data Availability Statement

The authors declare that the data supporting the findings and obtained during this research work are available within the paper.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Tamilnadu College of Engineering, Coimbatore, Tamilnadu, 641659, India

    Thiruvengadam Rajagopal

  2. Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, Tamilnadu, 641032, India

    Arvind Chakrapani

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  1. Thiruvengadam Rajagopal
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  2. Arvind Chakrapani
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Correspondence to Thiruvengadam Rajagopal.

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Rajagopal, T., Chakrapani, A. A Novel High-Performance Hybrid Full Adder for VLSI Circuits. Circuits Syst Signal Process 40, 5718–5732 (2021). https://doi.org/10.1007/s00034-021-01725-6

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