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Area and power delay product efficient level restored hybrid full adder (LR-HFA)

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Abstract

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, JCT College of Technology, Coimbatore, India

    V. J. Arulkarthick

  2. Department of Electronics and Communication Engineering, Tamilnadu College of Engineering, Coimbatore, India

    Rajagopal Thiruvengadam

  3. Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, India

    Chakrapani Arvind

  4. Department of Computer Science and Engineering, SNS College of Technology, Coimbatore, India

    K. Srihari

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  1. V. J. Arulkarthick
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  2. Rajagopal Thiruvengadam
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  3. Chakrapani Arvind
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  4. K. Srihari
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Correspondence to V. J. Arulkarthick.

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Arulkarthick, V.J., Thiruvengadam, R., Arvind, C. et al. Area and power delay product efficient level restored hybrid full adder (LR-HFA). Analog Integr Circ Sig Process 109, 165–172 (2021). https://doi.org/10.1007/s10470-021-01852-9

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  • DOI: https://doi.org/10.1007/s10470-021-01852-9

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