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A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques

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Abstract

This paper presents a new structure for high-resolution, low-power and wideband discrete time multi-stage (DT-MASH) sigma-delta (ΣΔ) modulators. It uses multi-bit digital input feed forward path (DFF) and noise coupling (NC) techniques. With the DFF technique, the modulator does not need a power-consuming analog adder at the quantizer input, and the number of comparators of the quantizer will be reduced significantly. Also, because of the reduced swing of the modulator’s integrators, low power integrators can be used. Using a second-order NC technique with no extra active block, the order of the modulator, which uses some paths between analog stages, is increased, and its performance is improved with zero-optimization of the modulator’s noise transfer function (NTF). Behavioral simulations and extensive mathematical analyses confirm the effectiveness of the proposed structure. The effect of the non-idealities in the DFF and NC paths were considered in the behavioral simulations. To examine its performance, a MASH 2–1 modulator was designed in the circuit level with a 180-nm CMOS technology and 1.8 V power supply. The integrators use a new op-amp switching technique to reduce total power consumption. With an over-sampling ratio (OSR) of 8 for the 10 MHz signal bandwidth, the proposed structure improves the signal-to-noise and distortion ratio (SNDR) by 28 dB compared with a conventional MASH 2–1 structure at approximately the same power consumption and very low complexity.

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References

  1. Morgado, A., del Río, R., & de la Rosa, J. (2008). Resonation-based cascade Σ∆ modulator for broadband low voltage A/D conversion. Electronics Letters, 44(2), 97–99

    Article  Google Scholar 

  2. Vleugels, K., Rabii, S., & Wooley, B. A. (2001). A 2.5-V sigma-delta modulator for broadband communications applications. IEEE Journal of Solid-State Circuits, 36(12), 1887–1899

    Article  Google Scholar 

  3. Van Ruermund, H. M., Casier, H., & Steyaert, M. (2006). Analog circuit design. Springer.

    Book  Google Scholar 

  4. Peng, J., Wang, J., & Tan, S. (2014). Optimal FIR filter design based on curve fitting approximation for uncertain 2–1 sigma-delta modulator. Circuits System and Signal Processing, 33(3), 885–894

    Article  Google Scholar 

  5. Ling, B. W., Ho, C. Y., Dai, Q., & Reiss, J. D. (2014). Reduction of quantization noise via periodic code for oversampled input signals and the corresponding optimal code design. Digital Signal Processing, 24, 209–222

    Article  Google Scholar 

  6. Yang, F., Gani, M., & Robust, H. (2007). approach for digital correction of cascaded Sigma Delta modulator. Circuits System and Signal Processing, 26(4), 607–618

    Article  MathSciNet  Google Scholar 

  7. Lee, K., Chae, J., Aniya, M., Hamashita, K., Takasuka, K., Takeuchi, S., & Temes, G. C. (2008). A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, 98 dB THD, and 79 dB SNDR. IEEE Journal of Solid-State Circuits, 43(12), 2601–2612

    Article  Google Scholar 

  8. Lee, K., Miller, M. R., & Temes, G. C. (2009). An 8.1 mW, 82 dB delta-sigma ADC with 1.9 MHz BW and 98 dB THD. IEEE Journal of Solid-State Circuits, 44(8), 2202–2211

    Article  Google Scholar 

  9. Temes GC (2008) New architectures for low-power delta-sigma analog-to-digital converter. IEEE Asia Pacific Conference on Circuits and Systems, pp. 1–6

  10. Silva, J., Moon, U., Steensgaard, J., & Temes, G. C. (2001). Wideband low-distortion delta-sigma ADC topology. Electronics Letters, 37(12), 737–738

    Article  Google Scholar 

  11. Q Liang, S Sai-Weng, U Seng-Pan et al (2017) A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2–1 MASH Σ∆ Modulator with Multirate Opamp Sharing. IEEE (TCAS1) 64: 1549–8328

  12. Pakash, J., Jose, B., Mathew, J., et al. (2017). A differential quantizer based error feedback modulator for analog to digital converters. IEEE Transactions Circuit System II: Express Briefs, 99, 1

    Google Scholar 

  13. Gutierrez E, Hernandez L, Cardes F (2017) VCO-based sturdy MASH ADC architecture. Electronics Letters 5th, 53, 1, 14–16

  14. Jamshidi, P., & Maymandi-Nejad, M. (2018). Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators Elsevier B.V. Integration, 1–10, 0167–9260

    Google Scholar 

  15. Shahghasemi, M., Yavari, M. (2016). MASH ΣΔ Modulators with a Noise-Shaped Two-Step ADC in the Second Stage. Integration, the VLSI Journal, 7 October.

  16. Khazaeili, B., & Yavari, M. (2017). A simple structure for MASH Σ∆ modulators with highly reduced in-band quantization noise. Springer Journal of Circuits, Systems, and Signal Processing, 36, 2125–2153

    Article  Google Scholar 

  17. Sebastian R, Prakash J, Jose BR, et al (2016) A multi-mode MASH Σ∆ modulator for low power wideband applications. Sixth International Symposium on Embedded Computing and System Design (ISED), 15–17: 87–90

  18. Sebastian, R., Prakash, J., Jose, B. R., et al. (2017). Multi-stage noise shaping Σ∆ modulator with enhanced noise shaping for low power wideband applications. Journal of Low Power Electron, 13(4), 661–668

    Article  Google Scholar 

  19. Kwak, Y. S., et al. (2018). A 72.9-dB SNDR 20-MHz BW 2–2 Discrete-time resolution-enhanced sturdy MASH delta-sigma modulator using source-follower-based integrators. IEEE Journal of Solid-State Circuits, 53(10), 2772–2782

    Article  Google Scholar 

  20. Schreier, R., & Temes, G. C. (2005). Understanding delta-sigma data converters. Wiley/IEEE Press.

    Google Scholar 

  21. Hamoui AA, Martin KW (2004) High-order multibit modulators and pseudo data-weighted-averaging in low- oversampling Σ∆ ADCs for broad-band applications. IEEE Transactions on Circuits Systems I 51(1), 72–85.

  22. Nam, K. Y., Lee, S. M., Su, D. K., & Woolley, B. A. (2005). A low-voltage low-power sigma-delta modulator for Broadband analog-to-digital conversion. IEEE Journal of Solid State Circuits, 40(9), 1855–1864

    Article  Google Scholar 

  23. Hamoui A, Sukhon M, Maloberti F (2008) Digitally-enhanced 2nd-order ΣΔ modulator with unity-gain signal transfer function. IEEE International Symposium. Circuits Systems 1664–1667.

  24. Hamoui A, Sukhon M, Maloberti F (2008) Digitally-enhanced high-order Σ∆ modulators. IEEE International. Conference Electronics Circuits Systems 161–170

  25. Kwon S, Maloberti F (2006) A 14mW multi-bit ΔΣ modulator with 82dB SNR and 86dB DR for ADSL2+. ISSCC Digest of Technical Papers, 161–170.

  26. Wang Y, Temes GC (2009) SD ADCs with second-order noise-shaping enhancement. IEEE International Midwest Symposium on Circuits and Systems, 345–348 ,August.

  27. Wei, R., & Yu, J. (2016). Multi-stage sigma-delta ADC with noise-coupling technology. IEICE Electronics Express, 13(23), 1–9

    Article  Google Scholar 

  28. Baird, R., & Fiez, T. (1995). Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging. IEEE Transactions on Circuits and Systems II, 42(12), 753–762

    Article  Google Scholar 

  29. Kwon S, Moon UK (2007) A high-speed delta-sigma modulator with relaxed DEM timing requirement. IEEE International Symposium on Circuits and Systems, 733–736.

  30. Sandner, C., Clara, M., Santner, A., Hartig, T., & Kuttner, F. (2005). A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS. IEEE Journal of Solid-State Circuits, 40(7), 1499–1505

    Article  Google Scholar 

  31. Haroun, M. A. N. (2014). Low-power high-speed high-resolution delta-sigma modulators for digital TV receivers in nanometer CMOS [dissertation]. Canada, Department of Electrical and Computer Engineering McGill University.

    Google Scholar 

  32. Gregorian, R. (1999). Introduction to CMOS op-amps and comparators. Wiley.

    Google Scholar 

  33. Razavi, B. (1995). Principles of data conversion system design. IEEE Press.

    Google Scholar 

  34. Kobayashi, T., Nogami, K., Shirotori, T., & Fujimoto, Y. (1993). A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE Journal of Solid-State Circuit, 28(4), 863–867

    Article  Google Scholar 

  35. Haroun M, Hamoui A (2013) A current-mirror opamp with switchable transconductances for low-power switched-capacitor integrators. in Proceedings IEEE International Symposium Circuits Systems 393–396.

  36. Lancioni W, Dualibe F (2018). Continuous Time Full-Feedforward MASH 2–2 Architecture for Sigma-Delta Modulators. IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS).

  37. Dessouky, M., & Kaiser, A. (2001). Very low-voltage digital-audio ΣΔ modulator with 88-dB dynamic range using local switch bootstrapping. IEEE Journal of Solid-State Circuits, 36(3), 349–355

    Article  Google Scholar 

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Correspondence to Tohid Moosazadeh or Reza Sabbaghi-Nadooshan.

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Fakhraie, H., Moosazadeh, T., Sabbaghi-Nadooshan, R. et al. A multi-stage sigma-delta modulator based on noise-coupling and digital feed-forward techniques. Analog Integr Circ Sig Process 108, 253–266 (2021). https://doi.org/10.1007/s10470-021-01877-0

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