Physics based compact modeling of symmetric double gate MOS transistors with high mobility III-V channel material
Introduction
Due to the aggressive scaling, power density inside the scaled device increases substantially which demands a proper thermal management scheme thereby increasing the production cost [1,2]. Power dissipation by a logic chip can be minimized by reducing supply voltage but that leads to degradation in switching characteristics. To mitigate this problem, researchers are looking for high mobility channel material where inversion charges can travel at a much higher speed than silicon thereby resulting in higher drive current at reasonably low supply voltages. The III-V compound semiconductors such as InAs, InGaAs, InSb, etc. are a promising candidate as an alternate channel material in the next generation scaled MOS devices due to their superior electron transportation such as low electron effective mass, high electron mobility, and high saturation velocity [3].
Although III-V channel MOSFETs show attractive transport properties, there are some inherent problems. Due to the higher permittivity of III-V materials, III-V MOSFET suffers from poor electrostatic integrity (EI) which results in higher short channel effects. By introducing ultra-thin body, multiple gate architecture and channel engineering, gate controllability and therefore EI can be improved [2]. Achieving a good quality interface is another one issue for III-V MOSFET. Literature survey reveals that with shows good interface quality with less trap density [4].
For circuit simulation purposes, a compact model of the device is essentially required. Also, compact models are an integral part of a process design kit (PDK). Due to the low effective mass and ultra-thin channel structure, III-V MOSFET shows stronger quantum confinement. As a result, electron energy split into multiple sub-bands [[5], [6], [7]]. In Silicon channel based MOSFET, due to comparatively higher effective mass, the quantum effect is insignificant and often that effect is introduced into the model in terms of correction scheme (charge centroid and modification in gate oxide thickness). However, those strategies are not applicable for III-V MOSFETs where Schrödinger and Poisson equation needs to be solved explicitly to obtain inversion charge and surface potential. This makes the model development task much harder than Silicon MOS devices. Moreover, the conduction band of III-V materials is strongly non-parabolic in nature and parabolic relation between energy-wave vector are not fully valid. Additionally, the mean free path of III-V materials is significantly higher than Silicon, and charge transport property is semi-ballistic in nature at shorter channel length. As a result, the velocity overshoot phenomenon takes place. A compact model of III-V MOSFET demands all these features that need to be incorporated accurately without increasing the computational burden.
Literature survey reveals that there are few attempts made on the development of a compact model of III-V MOSFET. Modeling of inversion charge and capacitance of III-V double gate MOSFET reported in Refs. [[8], [9], [10], [11]]. The modeling of surface potential and charge inside a potential well is reported in Ref. [12]. In that work, the authors have used a triangular potential well to model the quantum well. A first order perturbation method has been applied to correct sub-band energies and wavefunctions in presence of applied electric field. The surface potential and inversion charge is derived using numerical approach. In Ref. [13], a compact model of double-gate MOSFET is reported where the drain current and terminal charges are derived using polynomial based interpolation scheme. In Ref. [14], a surface potential-based compact drain current model of III-V on Insulator MOS transistor is reported where the relation between Fermi level and inversion charge is represented using one interpolation function. The conduction band non-parabolicity and velocity overshoot effect are not included in all these above-mentioned models. In another work, a compact model of inversion charge with quantum capacitance and drain current is reported in Ref. [15], where the contribution of 2nd sub-band and band non-parabolicity has been incorporated in form of a correction factor. In Ref. [16], a charge based drain current model of buffered InAs-on-insulator MOS transistor is reported. The velocity overshoot effect is included by modifying the saturation velocity by a channel length-dependent saturation velocity. This model also includes the band non-parabolicity effect. However, this model is primarily applicable to buffered III-V-on-insulator transistors with single gate operation.
In this work, we propose a compact model of the surface potential, inversion charge and drain current of a symmetric double-gate MOS transistor with high mobility III-V channel material. The unique attribute of our work is as follows. We solve 1-D Schrödinger and Poisson equation explicitly along confinement direction to find sub-band energy, inversion charge density, and potential. A 1st order correction to the sub-band energy, effective mass and 2-D density of states (DOS) due to band non-parabolicity effect has been incorporated. Velocity overshoot effect has been incorporated by modifying saturation velocity () using a channel length-dependent saturation velocity. The core model is free from any empirical parameters. The model predicted result has been validated against numerical simulation data for various channel thicknesses, different effective mass, and a wide range of bias voltages.
This article is organized in different sections. Section-1 describes the introduction part. Section-2 represents the model development framework. Section-3 contains the model implementation and validation with a professional numerical simulator. Finally, the conclusion is summarized in Section-4.
Section snippets
Device structure and model development framework
Fig. 1 (a) shows the device structure considered for analytical model development. In this work, we consider is the thickness of the device, is the physical channel length, and is the oxide thickness of front and back gates of the semiconductor device. In addition, we assume is at the center position of the channel thickness, and is at the start position of the channel. The potential well profile is shown in Fig. 1(b). All energy levels are measured with respect to the bottom
Device simulation framework
For III-V compound semiconductor materials, all physical parameters such as electron effective mass, band-gap energy, electron affinity and dielectric constant are estimated using Veggard's interpolation formula [25]. The device simulation is carried out with the help of Schrödinger-Poisson solver [17] and a commercial 2-D device simulator, SDEVICE from Synopsys Inc [26]. All simulations have been carried out at room temperature (T = 300K). To evaluate the electron density and surface potential
Conclusion
In this article, we have reported a core model for surface potential, inversion charge, and drain current of a double gate MOSFET with low effective mass III-V channel materials. The model correctly captures the variation in surface potential, sub-band energy, and inversion layer charge. The model predicted results have been validated with self-consistent Schrödinger-Poisson solver data along with commercial device simulator (TCAD) and a reasonable agreement has been achieved. Terminal charges
Author statement
Ho Le Minh Toan: Conceptualization, Methodology, Visualization, Investigation, Software, Validation, Writing- Original draft preparation. Subir Kumar Maity: Supervision, Writing- Reviewing and Editing.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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