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A dual-residue pipelined SAR ADC using only zero-crossing signals

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Abstract

This paper presents a dual-residue pipelined successive approximation register (SAR) A/D converter (ADC) that relaxes the accuracy requirement for residue amplifications and thus enables use of only zero-crossing (ZX) signals for the benefits of power efficiency and technology scalability. The dual-residue architecture is illustrated with design of an 11b two-step pipelined ADC consisting of 8b coarse and 5b fine (with 2b over-range) SAR sub-ADCs, which resolve 2b and 1b per SAR conversion cycle, respectively. Two ZX signals (or dual-residues) in opposite polarities automatically available in each 2b SAR cycle are sampled and held at the end of the coarse conversion for use as the full-scale reference for the fine SAR that quantizes a fixed input of zero. Simulations show that the ADC in 45 nm CMOS using typical open-loop circuits for inter-stage residue operation can achieve ENOB > 10 at 400 MS/s and Schreier FoM = 171.4 dB without residue gain calibration.

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The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgement

The authors acknowledge Global Foundries for providing the 45RFSOI PDK.

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Authors and Affiliations

  1. Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Xin Jin & Fa Foster Dai

  2. Broadcom Inc, Irvine, CA, 92618, USA

    Xin Jin & Hui Pan

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  1. Xin Jin
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  2. Hui Pan
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  3. Fa Foster Dai
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Correspondence to Xin Jin.

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Jin, X., Pan, H. & Dai, F.F. A dual-residue pipelined SAR ADC using only zero-crossing signals. Analog Integr Circ Sig Process 108, 229–239 (2021). https://doi.org/10.1007/s10470-021-01860-9

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