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Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification

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Abstract

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (W) and height/depth (H) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (ΔVT = VT, for –VT,rev ~ 0) and achieve voltage amplification (AV). The optimized conditions are found to be H = 19.3 nm and 24.3 nm to achieve the criterion with AV > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (FS). Tuning FS can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum FS value of 30 nm helps the FinFETs achieve capacitance matching with AV > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for HFinFET/WFinFET ~ 3 and Fs/HFinFET ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.

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Acknowledgements

The authors are grateful for the computing support received by the National Center for High-Performance Computing (NCHC), Taiwan.

Funding

This research was funded by the Ministry of Science and Technology (MOST 109-2218-E-003-003, MOST 109-2622-8-002-003, and MOST 109-2221-E-005-016).

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Authors and Affiliations

  1. Institute and Undergraduate Program of Electro-Optical Engineering, National Taiwan Normal University, Taipei, Taiwan

    K.-T. Chen, K.-Y. Hsiang, C.-Y. Liao, S.-H. Chang, F.-C. Hsieh, J.-H. Liu, S.-H. Chiang, H. Liang & M. H. Lee

  2. Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan

    K.-T. Chen & S. T. Chang

  3. Department of Electronics Engineering, Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan

    K.-Y. Hsiang

Authors
  1. K.-T. Chen
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  2. K.-Y. Hsiang
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  3. C.-Y. Liao
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  4. S.-H. Chang
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  5. F.-C. Hsieh
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  6. J.-H. Liu
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  7. S.-H. Chiang
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  8. H. Liang
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  9. S. T. Chang
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  10. M. H. Lee
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Contributions

KTC designed the overall architecture and contributed to the implementation and deployment of this work. KYH and CYL focused on the analysis of the results. SHC and FCH were mainly involved in the simulations. JHL, SHC, and HL focused on processing the results. STC was a consultant for this work. MHL was responsible for proposing the research topic, project administration, funding acquisition, reviewing the work, and preparation of the paper.

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Correspondence to S. T. Chang or M. H. Lee.

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Chen, KT., Hsiang, KY., Liao, CY. et al. Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification. J Comput Electron 20, 1209–1215 (2021). https://doi.org/10.1007/s10825-021-01701-y

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  • DOI: https://doi.org/10.1007/s10825-021-01701-y

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