Skip to main content
SpringerLink
Log in

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18

Similar content being viewed by others

References

  1. Fang X, Yu Y, Peng X (2019) "TSV Prebond Test Method Based on Switched Capacitors," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(1):205–218

  2. Hsu W, Kochte MA, Lee K (2017) Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. IEEE Trans Comput Aided Des Integr Circuits Syst 36(6):1004–1017

    Article  Google Scholar 

  3. Huang Y, Pan C, Lin S, Guo M (2018) Machine-Learning Approach in Detection and Classification for Defects in TSV-Based 3-D IC. IEEE Transactions on Components, Packaging and Manufacturing Technology 8(4):699–706

    Article  Google Scholar 

  4. "International Technology Roadmap for Semiconductors" (2013)

  5. Jang J, Cheong M, Kang S (2019) TSV Repair Architecture for Clustered Faults. IEEE Trans Comput Aided Des Integr Circuits Syst 38(1):190–194

    Article  Google Scholar 

  6. Kannan S, Kim B, Ahn B (2012) "Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects". J Electron Test 28, 39–51

  7. Katti G, Stucchi M, De Meyer K, Dehaene W (2010) Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs. IEEE Trans Electron Devices 57(1):256–262

    Article  Google Scholar 

  8. Kim J, Cho J, Kim J, Yook J-M, Kim JC, Lee J, Park K, Pak JS (2014) High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via. IEEE Transactions on Components, Packaging and Manufacturing Technology 4(4):697–707

    Article  Google Scholar 

  9. Koneru A, Kannan S, Chakrabarty K (2017) Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC) 13(4):1–23

    Article  Google Scholar 

  10. Lee Y, Kim J, Choi I, Kang S (2016) "A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs,". Proc. International SoC Design Conference (ISOCC), Jeju, 129–130

  11. Lee Y, Lim H, Kang S (2017) Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. IEEE Trans Comput Aided Des Integr Circuits Syst 36(10):1759–1763

    Article  Google Scholar 

  12. Lou Y, Yan Z, Zhang F et al (2012) Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods. J Electron Test 28:27–38

    Article  Google Scholar 

  13. Maity DK, Roy SK, Giri C (2018) "Identification of Faulty TSVs in 3D IC During Pre-Bond Testing,". Proc. 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID), Pune, 109–114

  14. Maity D, Roy S, Giri C, Rahaman H (2018) "Identification of Faulty TSV with a Built-In Self-Test Mechanism,". Proc. IEEE 27th Asian Test Symposium (ATS), Hefei, 1–6

  15. Maity DK, Roy SK, Giri C (2019) Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. J Electron Test 35:741–759

    Article  Google Scholar 

  16. Metzler C, Todri A, Bosio A, Dilillo L, Girard P, Virazel A (2012) "Through-Silicon-Via resistive-open defect analysis,". Proc. 17th IEEE European Test Symposium (ETS), Annecy, 1–1

  17. Noia B, Chakrabarty K, Marinissen EJ (2012) Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J Electron Test 28:103–120

    Article  Google Scholar 

  18. Papadopoulos S, Gerakis V, Tsiatouhas Y, Hatzopoulos A (2017) "Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs,". Proc. 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Thessaloniki , 1–6

  19. Rodríguez-Montañés R, Arumí D, Figueras J (2019) "Postbond Test of Through-Silicon Vias With Resistive Open Defects," in IEEE Transact Very Large Scale Integrat (VLSI) Syst 27(11):2596–2607

  20. Sung H, Cho K, Yoon K, Kang S (2017) "A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories," in IEEE Transact Very Large Scale Integrat (VLSI) Syst 22(11):2380–2387

  21. Ye F, Chakrabarty K (2012) "TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation,". Proc. DAC Design Auto Conference 2012, San Francisco, CA, 1024–1030

  22. You JW, Huang SY, Lin YH, Tsai MH, Kwai DM, Chou YF, Wu CW (2013) "In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis," in IEEE Transact Very Large Scale Integrat (VLSI) Syst, 21:(3):443–453.

  23. Yu Y, Fang X, Peng X (2020) A Post-Bond TSV Test Method Based on RGC Parameters Measurement. IEEE Trans Comput Aided Des Integr Circuits Syst 39(2):506–519

    Article  Google Scholar 

  24. Zhang B, Agrawal VD (2017) Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J Electron Test 33:573–589

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece

    Vasileios Gerakis & Alkis Hatzopoulos

  2. Department of Computer Science and Engineering, University of Ioannina, Ioannina, Greece

    Yiorgos Tsiatouhas

Authors
  1. Vasileios Gerakis
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Yiorgos Tsiatouhas
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Alkis Hatzopoulos
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Vasileios Gerakis.

Additional information

Responsible editor: E. J. Marinissen

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gerakis, V., Tsiatouhas, Y. & Hatzopoulos, A. A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs. J Electron Test 37, 191–203 (2021). https://doi.org/10.1007/s10836-021-05939-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-021-05939-z

Keywords

Search

Navigation