SPUF design based on Camellia encryption algorithm

Abstract

To meet the security requirements of resource-constrained systems, a software PUF (SPUF) scheme based on the encryption algorithm is proposed using the timing violation to generate the chip’s fingerprint. In this work, the Camellia encryption algorithm is selected and implemented via a semi-custom design flow to get the deviation of circuit delay. And then, the delay time of critical path of the proposed circuit is generated through static timing analysis. Using the overclocking frequency, the Camellia encryption algorithm circuit operates at timing violation status. We can collect the wrong response data of the simulation result at different input signals. The wrong data caused by timing violation can be defined as output of SPUF, which is the chip’s fingerprint. To improve the randomness, the multi-round operation of the Camellia is used to process the SPUF data. The experimental results show that the uniqueness of SPUF is 50.01%, the SPUF data passes the NIST test, and no additional hardware overhead is required.

Introduction

With the advent of the Internet of Things (IoT), ensuring secure communication among these devices is extremely important. Traditional measures use digital keys stored in non-volatile memory (NVM) [1], which is however vulnerable to attacks such as layout reverse engineering [2], micro-detection and other methods, to cause key exposure. Physical unclonable function (PUF) uses random variations introduced during the integrated circuit (IC) manufacturing process to generate high security keys that can resist various physical attacks. It can be used in a wide range of applications such as chip anti-counterfeiting, user authentication, protection of intellectual property (IP) [3], etc. Since the proposition of silicon PUFs [4], many well-performing PUFs have been proposed one after another, but their application in the IoT field is limited due to non-negligible power or area overhead.

PUFs are usually designed as standalone chips added to the target circuit or implemented on field programmable gate arrays (FPGAs), such as arbiter PUFs (APUFs) [5] and ring oscillator PUFs (RO PUFs) [6]. The APUF exploits random delays in the circuit caused by manufacturing deviation to generate the PUF response, while the RO PUF response depends on the frequency difference between two identical oscillators. Although researchers continue to improve this type of PUF [[7], [8], [9], [10]] to make its performance more superior, the additional area overhead is still unavoidable. The static random-access memory PUF (SRAM PUF) [11,12] is one way to solve the above problems. The SRAM PUF generates responses by extracting random power-up values of the SRAM cells. Since memory is widely present in commercial electronic products, SRAM PUF is more convenient in designing and does not need to consume additional hardware resources. However, its random feature relies on the power cycling, and not suitable for frequently switching power supply. MScanPUF [13] uses the uncertainty of data sampled from registers to generate PUF data in the case of timing violations, which solves the problem of memory-based PUF acquisition responses, but requires the addition of two 2-to-1 multiplexers to the original scan chain structure, resulting in additional costs. The microprocessor PUF [14] designs encoding rules to generate PUF responses base on differences in failure behaviors across different chips that execute one instruction multiple times under overclocking. The PUF does not require dedicated hardware overhead, but requires precise frequency variations and repeated execution of instructions with a small number of output response bits. On this basis, [15] exploits the difference of registers sampling data, which caused by the delay deviation of the inverter chain at a fixed frequency, to obtain PUF data, but additional inverter chains and registers are required.

To solve the above problems, a design of SPUF based on Camellia encryption algorithm is proposed in this paper. Unlike the PUF circuit that relies on additional circuit logic, the SPUF uses the path delay deviation in the hardware circuit of the encryption algorithm to obtain the response data without the need for dedicated hardware. First, the timing violation principle and circuit delay deviation are analyzed, and the relationship between timing violation and process parameter deviation is obtained. Then the semi-custom design flow based on standard cell is used to implement the algorithm hardware circuit and generate timing violations, followed by a combination of digital and analog simulation methods to extract PUF data. Finally, the performance of SPUF is evaluated under different frequencies of clock and different data signals.