Skip to main content
Log in

CMOS level shifters from 0 to 18 V output

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control logic supply VDD. Two application examples are presented: a composite switch to control negative stimuli voltage pulses, and a multi-channel programmable charge-pump voltage multiplier, aimed at charging the output capacitors of an IMD.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Maghsoudloo, E., Rezaei, M., Sawan, M., & Gosselin, B. (2017). A high-speed and ultra low-power subthreshold signal level shifter. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(5), 1164–1172.

    Article  Google Scholar 

  2. Matsuzuka, R., et al. (2017). An 80-mV-to-1.8-V conversion-range low-energy level shifter for extremely low-voltage VLSIs. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(8), 2026–2035.

    Article  Google Scholar 

  3. Lotfi, R., et al. (2018). Energy-efficient wide-range voltage level shifters reaching 4.2 fJ/transition. IEEE Solid-State Circuits Letters, 1(2), 34–37.

    Article  MathSciNet  Google Scholar 

  4. Thomas, S., Varghese, G. T. (2017). Design of optimum power, delay efficient level shifter for biomedical applications. In 2017 International Conference on Intelligent Computing, Instrumentation and Control Technologies (ICICICT) (pp. 219–222). Kannur, India.

  5. Novo, A., Gerosa, A., Neviani, A., Zanoni, E., Mozzi, A. (1999). Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 µm technology. In 25th European Solid-State Circuits Conference (ESSCIRC’99) (pp.386–389). Duisburg, Germany.

  6. Dommel, N., Lehmann, T., Wong, Y., Lovell, N., Byrnes-Preston, P., Suaning, G. (2006). Microelectronic retinal prosthesis: II. use of high-voltage CMOS in retinal neurostimulators. In IEEE EMBS Conference (pp.4651–4654). New York, USA.

  7. Gak, J., Arnaud, A., Miguez, M., Mandolesi, P. (2017). Blind range level shifters from 0 to 18V. In 8th Latin American Symposium on Circuits & Systems (LASCAS). Bariloche, Argentina.

  8. Luo, Z., & Ker, M. (2016). A high-voltage-tolerant and precise charge-balanced neuro-stimulator in low voltage CMOS process. IEEE Transactions on Biomedical Engineering, 10(6), 1087–1099.

    Google Scholar 

  9. Khorasani, M., et al. (2008). Low-power static and dynamic high-voltage CMOS level-shifter circuits. In 2008 IEEE International Symposium on Circuits and Systems (pp. 1946-1949). Seattle, WA.

  10. Kabirpour, S., & Jalali, M. (2020). A power-delay and area efficient voltage level shifter based on a reflected-output wilson current mirror level shifter. IEEE Transactions on Circuits and Systems II: Express Briefs, 67(2), 250–254.

    Article  Google Scholar 

  11. Prutchi, D., Norris, M. (2005). Cardiac pacing and defibrillation Design and development of medical electronic instrumentation. Wiley.

  12. CEN/CENELEC EN 45502–2 standard, Active implantable medical devices -- Part 2–1: Particular requirements for active implantable medical devices intended to treat bradyarrhythmia (cardiac pacemakers)”

  13. Merrill, D. R., Bikson, M., & Jefferys, J. G. (2005). Electrical stimulation of excitable tissue design of efficacious and safe protocols. Journal of Neuroscience Methods, 141(2), 171–198.

    Article  Google Scholar 

  14. Wong, L. S. Y., Hossain, S., Ta, A. (2004). A very low-power CMOS mixed-signal IC for implantable pacemaker applications. IEEE Journal of Solid-State Circuits, 32(12), 2446–2457.

    Article  Google Scholar 

  15. Miguez, M., Gak, J., Costa, G., Arnaud, A. (2012). A low-voltage, low-power 1.03V voltage reference for implantable medical devices. Procs. EAMTA’12 (pp. 47–51). Cordoba, Argentina.

  16. Novo, A., Gerosa, A., & Neviani, A. (2001). A sub-micron CMOS programmable charge pump for implantable pacemaker. Analog Integrated Circuits and Signal Processing, 27(3), 211–217.

    Article  Google Scholar 

  17. Luo, Z., Yu, L., & Ker, M. (2019). An efficient, wide-output, high-voltage charge pump with a stage selection circuit realized in a low-voltage cmos process. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(9), 3437–3444.

    Article  Google Scholar 

Download references

Acknowledgement

The authors of this work would like to thank ANII FMV_2017_136543 for its funding, that made possible this research.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Joel Gak.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gak, J., Miguez, M. & Arnaud, A. CMOS level shifters from 0 to 18 V output. Analog Integr Circ Sig Process 107, 617–628 (2021). https://doi.org/10.1007/s10470-021-01827-w

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-021-01827-w

Keywords

Navigation