Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Highlights

• This paper makes a systematic study of using the gm/ID method for initial sizing of the class of multi-stage Op Amps with Miller compensations.

• We propose methods to derive constraints from design equations to make the gm/ID-based sizing more accurate and less simulation hungry.

• We further propose heuristic sizing rules that are suited for application to multi-stage Op Amps for quickly working out acceptable sizing.

• We have validated the effectiveness of the initial sizing method by Op Amp examples containing different number of stages.

• The proposed initial sizing method can be potentially integrated in an auto-sizing tool.

Abstract

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.

Introduction

Device sizing (including biasing) is an integral part of CMOS analog integrated circuit (IC) design. Due to the high dimensionality of the sizing parameters involved in many sizing problems, the designer often has to spend a great deal of time on circuit sizing.

Continuous down-scaling of the device feature size has driven the researchers’ attention to the design of multi-stage operational amplifiers (Op Amps) or operational transconductance amplifiers (OTAs) that can offer higher gains without impairing the signal swing, see for example [[1], [2], [3], [4], [5], [6]]. While higher gains can be achieved by multi-stage designs, design on their frequency compensations arises as an imperative design challenge.

In practice, experienced circuit designers would normally devote effects on establishing design equations to develop design insights and guide sizing. As a matter of fact, circuit-level design equations derived from alternative current (ac) analysis are the key means for developing the frequency compensation strategies in multi-stage Op Amp design. Some authors proposed to apply graphical means to guide the frequency compensation design [7,8], but it still ends up with qualitative design equations to guide sizing. Evidently, multiple-loop frequency compensation induces additional inter-stage constraints on the pole-zero placement via design equations. Such design equations must also be incorporated in sizing to ensure frequency performance. Without such design equations, multiple blind SPICE iterations would have to be incurred.

Recently, several symbolic methods have been proposed for automatically generating design equations in the ac domain [9,10]. These methods are particularly suited to the design of multi-stage amplifiers in that the effort of manual derivation of the pole-zero design equations can be substantially reduced. It is important to note that most design equations, although approximate, are analytical characterization of the dominant interrelations among a portion of design parameters. Such analytical relations can effectively reduce the blindness in searching feasible sizing regions. Unfortunately, most data-driven sizing optimization methods proposed in the literature such as [[11], [12], [13]] did not make use of analytical design equations in their optimization routines. Data-driven performance modeling or causality inference requires simulation-expensive routines.

Design equations can not only offer design insights, but also effectively reduce the uncertainty in sizing. However, due to the large number of design parameters involved in many sizing problems, using the circuit-level design equations only cannot completely determine all device sizes. Deterministic mapping from numerically derived device operating conditions to the device dimensions (W and L) with high reliability must be considered in initial sizing.

A traditionally used sizing method is to apply the following current-voltage (I–V) equation (using an n-channel MOSFET as an example) [14].

$$I_D={\mu }_n{C}_{ox}\frac{W}{L}\left[\left(V_{GS}-V_{THn}\right)V_{DS}-\frac{1}{2}{V}_{DS}^2\right]$$

where C_ox is the gate oxide capacitance per unit area, μ_n is the mobility of n-type charge carriers, V_THn is the threshold voltage between the gate and source terminals, and W and L denote the channel width and effective channel length which are the sizing parameters of all MOSFETs throughout this paper. The aspect ratio always refers to W/L. Variables I_D, V_GS, and V_DS carry their usual meanings. For devices in saturation two equations derivable from the above I–V equation are

$$\frac{W}{L}=\frac{g_m^2}{2{\mu }_n{C}_{ox}{I}_D}$$

and

$$\frac{W}{L}=\frac{2I_D}{{\mu }_n{C}_{ox}{V}_{DSAT}^2}$$

(V_DSAT denoting the saturation drain-source voltage), which are frequently used in the traditional sizing procedures, such as [[15], [16], [17]]. However, as pointed out by Razavi [14], these equations are mainly for developing intuition in analog design, but do not bear rigor or accuracy for sizing. Accurate initial sizing still has to resort to rigorous device model equations implemented in most SPICE simulators.

Several earlier publications on multi-stage Op Amp design outlined manual sizing procedures [[15], [16], [17]], which used the circuit-level design equations for noise, power, signal range, and frequency response performance as well as the device-level equations (2), (3) for calculating the MOSFET dimensions. Due to the inaccuracy of the device equations, many SPICE iterations are required to correct the calculated sizes and biasing, whereas the numbers of the correction times were often not reported in those publications.

An alternative to the device size mapping from the known operating conditions is by adopting a numerical table lookup tactic that builds a numerical device model profile by sweeping a set of selective device parameters. The gm/ID method is one such method that has received wide attentions. It can be used as a substitute to the simplistic square-law equations with the hope of reducing SPICE iterations in initial sizing.

The gm/ID method was published quite early [18,19], but did not receive wide spreading attention until quite recently more sophisticated design cases have been addressed [[20], [21], [22]]. Although these works mainly dealt with the single-stage amplifier designs, the robustness of the gm/ID method in generating accurate sizing results has been demonstrated. As one may observe from the work by Aminzadeh [22], more robust sizing results can be obtained if more sophisticated gm/ID sweeping data including variational sweeping data are incorporated. However, so far application of the gm/ID method to the sizing of multi-stage Op Amps is still rare. In Chapter 6 of Jespers and Murmann's book [23] the sizing of a two-stage fully differential Op Amp with Miller capacitor and nulling resistor compensation was developed by the gm/ID method. The sizing method developed there was targeted at applications to the switched-capacitor data converter circuits. Therefore, design specifications on the slew and settling metrics were more emphasized, for which the gain-bandwidth product (GBW) metric became the main design target. The authors introduced several MATLAB routines for running two-dimensional sweeping-based optimizations on several selected sizing parameters. However, since the proposed sizing method was centered on a specific circuit structure, it did not guarantee that the outlined highly customized sizing procedure could be easily extended to other multi-stage amplifier configurations.

The gm/ID sizing method promoted in this paper is targeted at initial sizing, which has its importance in several aspects. In practice, an initial sizing result can offer the designer with a good insight on what part of a circuit would need more attention for optimization. On the other hand, if several attempts of initial sizing could not give rise to a satisfactory circuit performance, it would be a good indication that probably the current circuit topology possesses certain defect. We illustrate the role of initial sizing in Fig. 1, showing that an efficient initial sizing method can not only benefit a subsequent sizing optimizer but also improve the circuit topology design in a topological synthesis loop.

Regarding sizing optimization, numerous previous works have made dedicated researches [13,[24], [25], [26], [27], [28], [29], [30], [31], [32]], with the majority of them requiring a sheer number of simulations. Fairly speaking, promising initial sizing results can substantially reduce the number of SPICE iterations in the subsequent optimization phase.

A systematic initial sizing procedure is developed in this paper for the class of multi-stage Op Amps (or OTAs) with the following features:

• We apply the gm/ID method with a variety of design equations to determine the initial sizing of a multi-stage Op Amp in a stage by stage fashion.

• We assume that the parasitic device capacitances are insignificant comparing to the compensation and load capacitors. Hence, we use mainly the direct current (dc) gm/ID sweeping curves in sizing to avoid fine tuning the parasitic effects on the frequency response.

• We adopt small-signal design equations (on gain, poles, zeros, GBW, phase margin, common-mode gain, etc.) together with other topologically derived design equations (on noise, common-mode range, and slew rate, etc.) to develop sizing constraints.

• We customize the ac design equations with the gm/ID variables to infer constraints on the gm/ID values from the design equations and the specification metrics.

• We also propose less expensive SPICE iteration methods to refine the improperly inferred sizing results by a few heuristic sizing rules.

Initial sizing by gm/ID for multi-stage Op Amps with the above listed features have not been completely addressed in a systematic way yet previously. A stage-by-stage initial sizing method is intuitive (i.e., totally based on circuit topologies), easy to follow by the beginners, and deterministic (requiring less SPICE iterations). More importantly, a sizing procedure so developed can be more easily adapted to automation once design equations can be automatically generated. The reader is referred to the works by Shi [9,10,33] for the recent progress.

This paper is organized as follows. In section 2 we discuss several commonly used amplifier stages and the gm/ID method currently well-known for sizing. Then in section 3 we develop procedural sizing methods for single-stage and multiple-stage amplifiers. Methods of how to customize the circuit-level design equations amenable to gm/ID constraints are discussed there, together with detailed sample designs on a one-stage, a two-stage, and a three-stage Op Amp. Finally, this paper is concluded in section 4.