Abstract
This paper proposes a novel geometric programming based formulation to solve a gate-sizing and retiming problem in the context of circuit optimization. The gate-sizing aspect of the problem involves continuous variables while the retiming problem involves the placement of registers in the circuit and can be naturally modeled using discrete variables. Our formulation is solved using first-order convex programming. We show promising experimental results on industrial circuits. We also investigate formally the computational complexity of the problem. To our knowledge, this is the first effort that solves this problem in a single optimization framework.
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References
Boyd S, Kim S-J, Patil D, Horowitz M (2005) Digital circuit optimization via geometric programming. Oper Res 53(6):899–932
Butnariu D, Censor Y, Gurfil P, Hadar E (2008) On the behavior of subgradient projections methods for convex feasibility problems in euclidean spaces. SIAM J Optim 19(2):786–807
Chuang W, Sapatnekar SS, Hajj IN (1993) A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. In: International conference on computer-aided design
Coudert O (1997) Gate sizing for constrained delay/power/area optimization. IEEE Trans VLSI, pp 465–472
DePierro AR, Iusem AN (1985) A simultaneous projections method for linear inequalities. Linear Algebra Appl, pp 243–253
Fishburn J, Dunlop A (1985) Tilos: a posynomial programming approach to transistor sizing. In: IEEE international conference on computer-aided design, pp 326–328
Fishburn JP (1990) Clock skew optimization. IEEE Trans Comput
Hurst A, Mischenko A, Brayton RK(2007) Minimizing implementation costs with end-to-end retiming. In: International workshop on logic sysnthesis
Jaggi M (2011) Convex optimization without projection steps. arXiv preprint arxiv:1108.1170
Joshi S, Boyd S (2008) An efficient method for lareg-scale gate sizing. IEEE Trans Circuits Syst-I 55:2760–2773
Kondamadugula S, Naidu SR (2019) Variation-aware parameter based analog yield optimization methods. Analog Integr Circ Sig Process 99:123–132
Leiserson CE, Saxe JB (1983) Optimizing synchronous systems. J VLSI Comput Syst, pp 41–67
Leiserson CE, Saxe JB (1991) Retiming synchronous systems. Algorithmica 6(1):5–35
Li WN (1993) Strongly np-hard discrete gate sizing problems. In: IEEE international conference on computer design
Naidu SR (2015) Geometric programming formulation for gate sizing with pipelining constraints. In: Proceedings of the international conference on VLSI design, pp 452–457
Purushothaman A, Parikh CD (2015) A new delay model and geometric programming-based design automation for latched comparators. Circuits Syst Signal Process, pp 2749–2764
Rajeswari P, Shekar G, Devi S, Purushothaman A (2018) Geometric programming based power optimization and design automation for a digitally controlled pulse width modulator. Circuits Syst Signal Process, pp 4049–4064
Roy S, Liu D, Singh J, Um J, Pan DZ (2016) Osfa: a new paradigm of aging aware gate-sizing for power/performance optimizations under multiple operating conditions. IEEE Trans Comput-Aided Des Integr Circuits Syst
Sabet MA, Ghavami B, Raji M (2017) A scalable solution to soft error tolerant circuit design using partitioning-based gate sizing. IEEE Trans Reliab
Satyamurthy H, Sapatnekar SS, Fishburn JP (1998) Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans Comput-Aided Des Integr Circuits Syst
Sutherland I, Sproull B, Harris D (1999) Logical effort: designing fast CMOS circuits. Morgan-Kaufmann, San Francisco
Wang J, Das D, Zhou H(2009) Gate sizing by lagrangian relaxation revisited. IEEE Trans Comput-Aided Des Integr Circuits Syst, pp 1071–1084
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Naidu, S.R. A convex programming solution for gate-sizing with pipelining constraints. Optim Eng 23, 947–982 (2022). https://doi.org/10.1007/s11081-021-09616-0
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DOI: https://doi.org/10.1007/s11081-021-09616-0