A new hardware Trojan detection technique using deep convolutional neural network

Highlights

• A new partial RE based HT detection technique using the DCNN model has been proposed.

• A new DCNN model architecture is proposed to perform automatic and relevant feature extraction from IC images.

• Proposed two new metrics and stopping condition method avoid overtraining of the DCNN model effectively.

• The proposed technique provides high detection accuracy on Trust-Hub and synthetic ISCAS benchmarks.

Abstract

The involvement of external vendors in semiconductor industries increases the chance of hardware Trojan (HT) insertion in different phases of the integrated circuit (IC) design. Recently, several partial reverse engineering (RE) based HT detection techniques are reported, which attempt to reduce the time and complexity involved in the full RE process by applying machine learning or image processing techniques in IC images. However, these techniques fail to extract the relevant image features, not robust to image variations, complicated, less generalizable, and possess a low detection rate. Therefore, to overcome the above limitations, this paper proposes a new partial RE based HT detection technique that detects Trojans from IC layout images using Deep Convolutional Neural Network (DCNN). The proposed DCNN model consists of stacking several convolutional and pooling layers. It layer-wise extracts and selects the most relevant and robust features automatically from the IC images and eliminates the need to apply the feature extraction algorithm separately. To prevent the over-training of the DCNN model, a new stopping condition method and two new metrics, namely Accuracy difference measure (ADM) and Loss difference measure (LDM), are proposed that halts the training only when the performance of our model genuinely drops. Further, to combat the issue of process variations and fabrication noise generated during the RE process, we include noisy images with varying parameters in the training process of the model. We also apply the data augmentation and regularization techniques in the model to address the issues of underfitting and overfitting. Experimental evaluation shows that the proposed technique provides 99% and 97.4% accuracy on Trust-Hub and synthetic ISCAS dataset, respectively, which is on-an-average 15.83% and 21.69% higher than the existing partial RE based techniques.

Introduction

Due to the huge requirements and the increasing complexities of the integrated circuit (IC) design, force the semiconductor industries to incorporate either third party Intellectual property cores (3PIP) or external vendors during the different phases of the IC supply chain. The involvement of these external parties may speed up the process and lessen the cost but also raises severe security concerns, including Hardware Trojan (HT), IP piracy, IC counterfeiting, IC overbuilding, and Reverse engineering [1]. Among all these threats, HT is the most dangerous due to its stealthy nature [2], [3]. Its consequences are very harmful and life-threatening for critical and sensitive applications such as Internet of Things (IoT) [4], [5], autonomous driving [6], surveillance systems [7], defense and mission-critical applications [8], [9]. An adversary can insert HT during the design and fabrication phase of the IC by either modifying the gate-level netlist or by manipulating the lithographic masks in the form of addition of gates, deletion of gates, and modification of size/parameters of gates (i.e., Parametric Trojans) [10], [11]. This malicious modification is triggered by rare condition and can change the functionality of the circuit, leak sensitive information, reduce the reliability, and cause a denial of service (DoS) [12].

Therefore, several countermeasures are reported in the literature that attempts to detect the Trojan during pre-silicon, and post-silicon IC phases [9], [13], [14]. However, in this paper, we are only concerned with the untrusted foundry problem, where an adversary can insert the Trojans during IC fabrication. Existing post-silicon techniques such as test pattern generation (TPG) and side-channel analyses (SCA) are either use several test patterns to activate the Trojans or measure various circuit parameters such as current, power, etc. for detection. However, TPG based approaches fail to detect large Trojans as it is difficult to generate a large number of test patterns to activate them. Whereas SCA based approaches are either rely on golden IC during detection or golden model-free, but fail to detect the small Trojans because they are vulnerable to process variations and fabrication noise [9], [13]. Hence, the aforementioned post-silicon techniques cannot cover all types of Trojans and possess a low detection rate. Recently several partial reverse engineering (RE) based techniques are also reported [15], which reduces the time and complexity involved in the full RE process [16], [17]. These techniques [18], [19], [20] extract the IC images and uses machine learning (ML)/image processing techniques to perform HT detection.

Bao et al. [18] proposed one-class support vector machine (SVM) based approach in which manual feature extraction takes place by comparing the IC layout image with golden IC image and five features are extracted to train the classifier for detection. Similarly, Abdurrahman et al. [21] proposed the Adaboost classifier-based approach in which they utilize the handcrafted feature selection algorithm HAAR to extract the features from IC schematic. However, both the manual and handcrafted features are not effective and highly affected by image variations. Moreover, manual feature extraction is a very complicated and time-consuming process, whereas handcrafted features are domain-dependent rule-based features selected by the experts, thus less effective for other domains. Further, they use shallow ML algorithms for detection which are less generalizable thus prone to underfitting/overfitting.

Therefore, to overcome the above-stated problems, we propose a robust partial RE based HT detection technique using Deep Convolutional Neural Network (DCNN). DCNN model have marked their success in the area of computer vision such as image classification [22], [23], object detection [24], [25], semantic segmentation [26] etc. It achieves state-of-the-art performance in multiple domains such as information security [27], remote sensing [23], medical field [28], [29] emotion recognition [30] and target detection [31] etc. by beating traditional handcrafted methods [32], [33]. The proposed DCNN model is different from ML/DL models because it contains the powerful feature extraction phase in its architecture, which uses the convolution operation rather than matrix multiplication. The inbuilt feature extraction process of the DCNN model is purely mathematical rather than domain-specific due to which it can extract the features from the images of any domain without requiring a handcrafted algorithm or golden IC reference. The reason behind its remarkable performance is the use of several convolutional and pooling layers, which perform the local connectivity and down-sampling to extract the relevant, invariant and non-linear features automatically in a hierarchical manner. The convolutional layer performs the convolution operation between the image and different kernels by establishing the local connection with the image subpart, which results in various unique feature maps. Max-pooling layer then reduces the size of each feature map by extracting the maximum information from it and provides partial and translation invariance, which makes the extracted features robust to any variation. All the feature maps are fed to the classification phase, which uses fully connected NN to learn these features and finally detect the IC as Trojan free, or Trojan inserted. To summarize, we have proposed a new DCNN model based HT detection technique and algorithm in this paper that accurately detects Trojans from IC layout images generated by partial RE. The major contributions are given as follows:

• A new DCNN model architecture is proposed that automatically extracts the relevant features from the IC layout images, even in the presence of any image and noise variations.

• A new training stopping condition method is proposed which uses two proposed metrics namely Accuracy difference measure (ADM) and Loss difference measure LDM to avoid the over-training of DCNN model.

• Experimental evaluation on synthetic ISCAS and Trust-Hub benchmarks provides on an average 97.4% and 99% accuracy, respectively.

The rest of the paper is organized as follows: Section 2 gives literature review analysis of existing HT detection techniques. Section 3 explains our proposed HT detection technique which includes proposed model architecture, stopping condition method and HT detection algorithm. Experimental results and comparative analysis is presented in Section 4. Finally, Section 5 concludes the paper.