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Fault Detection and Tolerance of a Hybrid Five Level Inverter

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Iranian Journal of Science and Technology, Transactions of Electrical Engineering Aims and scope Submit manuscript

Abstract

Multilevel inverters (MLIs) have received a significant attention in literature due to advent of various topologies utilising power semiconductor switches with reduced voltage stress. However, the increased component count and susceptible nature of semiconductor components increase the chance of failure in inverter. The fault in power switches, either open circuit or short circuit, if persist for long time may result in complete system shutdown. This damage can be avoided by detecting and diagnosing the fault in less period of time to continue the healthy operation. The present paper studies an open-circuit fault detection method on conventional five-level NPC inverter topology with output voltage waveform analysis by discrete wavelet packet transform (DWPT) and classifying the fault location by artificial neural network (ANN). The strategy to tolerate both abovementioned type of failure on any location after detection is proposed by implementing a novel redundant architecture in conventional five-level inverter. This architecture has an advantage of utilising less device count to tolerate fault on single as well as multiple switch combinations. The proposed work is studied in MATLAB/Simulink and validated experimentally.

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Correspondence to Guruvulu Naidu Ponnada.

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Ponnada, G.N., Babu, C.S., Satyanarayana, S. et al. Fault Detection and Tolerance of a Hybrid Five Level Inverter. Iran J Sci Technol Trans Electr Eng 45, 895–904 (2021). https://doi.org/10.1007/s40998-021-00415-y

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  • DOI: https://doi.org/10.1007/s40998-021-00415-y

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