Abstract
Workfunction variation (WFV) in a high-k/titanium metal gate stack vertical tunnel field-effect transistor (FET) with a delta-doped layer in the germanium source is explored using technology computer-aided design simulations. The field-induced quantum confinement effect is also evaluated for the vertical tunnel FET. The impact of the gate area on various electrical parameters such as the ON-current (σION), OFF current (σIOFF), current ratio [σ(ION/IOFF)], subthreshold swing (σSS), threshold voltage (σVT), and analog performance parameters such as the total gate capacitance (σCgg), transconductance (σgm), and cutoff frequency (σfT) due to WFV of the titanium gate metal is evaluated. The results show that the variability in ION and IOFF increases when decreasing the overall transistor gate area for different metal grain sizes. In addition, the variations in the subthreshold swing and threshold voltage also decrease for a larger gate area. The distributions of the electrical parameters show that, when the grain size is comparable to the gate dimension, the distribution is not Gaussian bounded. In addition, the plot of the ratio of the average grain size to the gate area reveals that a slope of more than ~ 120 mV is attained.
Similar content being viewed by others
References
Brown, G.A., Zeitzoff, P.M., Bersuker, G., Huff, H.R.: Scaling CMOS: materials & devices. Mater. Today 7, 20–25 (2004)
Bernstein, K., Cavin, R.K., Porod, W., Seabaugh, A., Welser, J.: Device and architecture outlook for beyond CMOS switches. Proc. IEEE 98, 2169–2184 (2010)
Bohr, M.T., Young, I.A.: CMOS scaling trends and beyond. IEEE Micro 37, 20–29 (2017)
Tura, A., Woo, J.C.S.: Performance comparison of silicon steep subthreshold FETs. IEEE Trans. Electron Devices 57, 1362–1368 (2010)
Ionescu, A.M., Riel, H.: Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479, 329–337 (2011)
Villalon, A., Royer, C.L., Casse, M., Cooper, D., Hartmann, J.M., Allain, F., Tabone, C., Andrieu, F., Cristoloveanu, S.: Experimental investigation of the tunneling injection boosters for enhanced ION ETSOI tunnel FET. IEEE Trans. Electron Devices 60, 4079–4084 (2013)
Bhushan, B., Nayak, K., Rao, V.R.: DC compact model for SOI tunnel field-effect transistors. IEEE Trans. Electron Devices 59, 2635–2642 (2012)
Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007)
Goswami, R., Bhowmick, B., Baishya, S.: Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattices Microstruct. 86, 342–354 (2015)
Choi, W.Y., Lee, W.: Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices 57, 2317–2319 (2010)
Sharma, A., Goud, A.A., Roy, K.: GaSb-InAs n-TFET with doped source underlap exhibiting low subthreshold swing at sub-10-nm gate-lengths. IEEE Electron Device Lett. 35, 1221–1223 (2014)
Raad, B.R., Nigam, K., Sharma, D., Kondekar, P.N.: Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlattices Microstruct. 94, 138–146 (2016)
Archarya, A., Solanki, A.B., Glass, S., Zhao, Q.T., Anand, B.: Impact of gate-source overlap on the device/circuit analog performance of line TFETs. IEEE Trans. Electron Devices 66, 4081–4086 (2019)
Liu, C., Ren, Q., Chen, Z., Zhao, L., Liu, C., Liu, Q., Yu, W., Liu, X., Zhao, Q.T.: A T-shaped SOI tunneling field-effect transistor with novel operation modes. IEEE J. Electron Devices Soc 7, 1114–1118 (2019)
Yang, S., Lv, H., Lu, B., Yan, S., Zhang, Y.: A novel planar architecture for heterojunction TFETs with improved performance and its digital application as an inverter. IEEE Access 8, 23559–23567 (2020)
Kumar, N., Raman, A.: Novel design approach of extended gate-on-source based charge-plasma vertical-nanowire TFET: proposal and extensive analysis. IEEE Trans. Nanotechnol. 19, 421–428 (2020)
Vanlalawpuia, K., Bhowmick, B.: Investigation of a Ge-source vertical TFET with delta-doped layer. IEEE Trans. Electron Devices 66, 4439–4445 (2019)
Vandenberghe, W.G., Sorée, B., Magnus, W., Groeseneken, G., Fischetti, M.V.: Impact of field-induced quantum confinement in tunneling field-effect devices. Appl. Phys. Lett. 98, 143503 (2011)
Walke, A.M., Verhulst, A.S., Vandooren, A., Verreck, D., Simoen, E., Rao, V.R., Groeseneken, G., Collaert, N., Thean, A.V.Y.: Part I: Impact of field-induced quantum confinement on the subthreshold swing behavior of line TFETs. IEEE Trans. Electron Devices 60, 4057–4064 (2013)
Padilla, J.L., Alper, C., Gámiz, F., Ionescu, A.M.: Assessment of field-induced quantum confinement in heterogate germanium electron–hole bilayer tunnel field-effect transistor. Appl. Phys. Lett. 105, 082108 (2014)
Beneventi, G.B., Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Optimization of a pocketed dual-metal-gate TFET by means of TCAD simulations accounting for quantization-induced bandgap widening. IEEE Trans. Electron Devices 62, 44–51 (2015)
Padilla, J.L., Alper, C., Gamiz, F., Ionescu, A.M.: Quantum mechanical confinement in the fin electron-hole bilayer tunnel field-effect transistor. IEEE Trans. Electron Devices 63, 3320–3326 (2016)
Datta, S., Dewey, G., Doczy, M., Doyle, B.S., Jin, B., Kavalieros, J., Kotlyar, R., Metz, M., Zelick, N., Chau, R.: High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack. IEEE Int. Electron Devices Meeting 2003, 28.1.1–4 (2003)
Hobbs, C.C., Fonseca, L.R.C., et al.: Fermi-level pinning at the polysilicon/metal oxide interface: part I. IEEE Trans. Electron Devices 51, 971–977 (2004)
Gusev, E.P., Narayanan, V., Frank, M.M.: Advanced high-k dielectric stacks with polySi and metal gates: recent progress and current challenges. IBM J. Res. Dev. 50, 387–410 (2006)
Avci, U.E., Rios, R., Kuhn, K., Young, I.A.: Comparison of performance, switching energy and process variations for the TFET and MOSFET in logic. Proc. Symp. VLSI Tech., 124–125 (2011)
Leung, G., Chui, C.O.: Stochastic variability in silicon double-gate lateral tunnel field-effect transistors. IEEE Trans. Electron Devices 60, 84–91 (2013)
Dadgour, H., Endo, K., De, V., Banerjee, K.: Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability, 2008 IEEE International Electron Devices Meeting, San Francisco, CA, 1–4 (2008)
Dadgour, H.F., Endo, K., De, V.K., Banerjee, K.: Grain-Orientation induced work function variation in Nanoscale metal-gate transistors—part I: Modeling, analysis, and experimental validation. IEEE Trans. Electron Devices 57, 2504–2514 (2010)
Dadgour, H.F., Endo, K., De, V.K., Banerjee, K.: Grain-Orientation induced work function variation in Nanoscale metal-gate transistors—Part II: Implications for Process, Device, and Circuit Design. IEEE Trans. Electron Devices 57, 2515–2525 (2010)
Rasouli, S.H., Xu, C., Singh, N., Banerjee, K.: A physical model for work-function variation in ultra-short channel metal-gate MOSFETs. IEEE Electron Device Lett. 32, 1507–1509 (2011)
Nawaz, S.M., Dutta, S., Chattopadhyay, A., Mallik, A.: Comparison of random dopant and gate-metal workfunction variability between junctionless and conventional FinFETs. IEEE Electron Device Lett. 35, 663–665 (2014)
Nam, H., Lee, Y., Park, J.D., Shin, C.: Study of work-function variation in high-κ/metal-gate gate-all-around nanowire MOSFET. IEEE Trans. Electron Devices 63, 3338–3341 (2016)
Saha, R., Bhowmick, B., Baishya, S.: Deep insights into electrical parameters due to metal gate WFV for different gate oxide thickness in Si step FinFET. IET Micro Nano Lett. 14, 384–388 (2019)
Choi, K.M., Choi, W.Y.: Work-function variation effects of Tunneling field-effect transistors (TFETs). IEEE Electron Device Lett. 34, 942–944 (2013)
Lee, Y., Nam, H., Park, J.D., Shin, C.: Study of work-function variation for high-k/metal-gate Ge-source tunnel field-effect transistors. IEEE Trans. Electron Devices 62, 2143–2147 (2015)
Saha, R., Bhowmick, B., Baishya, S.: Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET. Microelectron. Eng. 214, 1–4 (2019)
Guide, S.D.U.: Synopsys Inc. Mountain View, CA (2016)
Kao, K.H., Verhulst, A.S., Vandenberghe, W.G., Sorée, B., Groeseneken, G., Meyer, K.D.: Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans. Electron Devices 59, 292–301 (2012)
Kim, S.H., Kam, H., Hu, C., Liu, T.J.K.: Germanium-source tunnel field effect transistors with record high ION/IOFF. Proc. Symp. VLSI Technol., 178–179 (2009)
Johnson, H.T.: Effects of stress on formation and properties of semiconductor nanostructures. Material Substructures in Complex Bodies, 284–313 (2007)
Boucart, K., Riess, W., Ionescu, A.M.: Lateral strain profile as key technology booster for all-silicon tunnel FETs. IEEE Electron Device Lett. 30, 656–658 (2019)
Guo, Q., Dib, Z., Lagallyc, M.G., Mei, Y.: Strain engineering and mechanical assembly of silicon/germanium nanomembranes. Mater. Sci. Eng. R 128, 1–31 (2018)
Richter, S., Sandow, C., Nichau, A., Trellenkamp, S., Schmidt, M., Luptak, R., Bourdelle, K.K., Zhao, Q.T., Mantl, S.: Ω-Gated silicon and strained silicon nanowire array tunneling FETs. IEEE Electron Device Lett. 33, 1535–1537 (2012)
Chen, X., Tan, C.M.: Modeling and analysis of gate-all-around silicon nanowire FET. Microelec. Reliab. 54, 1103–1108 (2014)
Sung, P.J., Cho, T.C., Hou, F.J., Hsueh, F.K., Chung, S.T., Lee, Y.J., Current, M.I., Chao, T.S.: High performance uniaxial tensile strained n-channel JL SOI FETs and triangular JL bulk FinFETs for nano-scaled applications. IEEE Trans Electron Devices 64, 2054–2060 (2017)
Wang, W., Hwang, J., Xuan, Y., Ye, P.D.: Analysis of electron mobility in inversion-mode MOSFETs. IEEE Trans. Electron Devices 58, 1972–1978 (2011)
Pala, M.G., Esseni, D., Conzatti, F.: Impact of interface traps on the IV curves of InAs tunnel-FETs and MOSFETs: A full quantum study. IEDM Tech. Dig., 6.6.1–6.6.4 (2012)
Qiu, Y., Wang, R., Huang, Q., Huang, R.: A comparative study on the impacts of interface traps on tunneling FET and MOSFET. IEEE Trans. Electron Devices 61, 1284–1291 (2014)
Padilla, J.L., Bailon, C.M., Alper, C., Gamiz, F., Ionescu A.M.: Confinement-induced InAs/GaSb heterojunction electron–hole bilayer tunneling field-effect transistor. Appl. Phys. Lett. 112, 182101 (2018)
Ohmori, K., Matsuki, T., Ishikawa, D., Morooka, T., Aminaka, T., Sugita, Y., Chikyow, T., Shiraishi, K., Nara, Y., Yamada, K.: Impact of additional factors in threshold voltage variability of metal/high-k gate stacks and its reduction by controlling crystalline structure and grain size in the metal gates. Proc. IEEE IEDM, 1–4 (2008)
Nam, H., Shin, C.: Study of high-k/metal-gate work-function variation using Rayleigh distribution. IEEE Electron Devices Lett. 34, 532–534 (2008)
Acknowledgements
This publication is an outcome of the R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Government of India, being implemented by Digital India Corporation (formerly Media Lab Asia).
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Vanlalawmpuia, K., Bhowmick, B. Study on induced work-function variation of titanium metal gate on various electrical parameters for delta-doped layer germanium source vertical tunnel FET. J Comput Electron 20, 1137–1146 (2021). https://doi.org/10.1007/s10825-021-01686-8
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-021-01686-8