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Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

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Abstract

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

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Acknowledgements

The authors would like to thank the financial support of ANII, CSIC and CAP, Universidad de la República.

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Authors and Affiliations

  1. Instituto de Ingeniería Eléctrica, Facultad de Ingeniería, Universidad de la República, Montevideo, Uruguay

    Francisco Veirano, Pablo Castro Lisboa, Pablo Pérez-Nicoli & Fernando Silveira

  2. LTCI, Télécom ParisTech, Université Paris-Saclay, 75013, Paris, France

    Lirida Naviner

Authors
  1. Francisco Veirano
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  2. Pablo Castro Lisboa
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  3. Pablo Pérez-Nicoli
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  4. Lirida Naviner
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  5. Fernando Silveira
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Correspondence to Francisco Veirano.

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Veirano, F., Lisboa, P.C., Pérez-Nicoli, P. et al. Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters. Analog Integr Circ Sig Process 109, 271–282 (2021). https://doi.org/10.1007/s10470-021-01810-5

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  • DOI: https://doi.org/10.1007/s10470-021-01810-5

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