Dynamic resistance variation mapping technique for defect isolation
Introduction
Conventional Optical Beam Induced Resistance Change (OBIRCH) uses a constant voltage bias and current detection configuration to monitor current changes by using a low noise and high gain current amplifier. Current changes are consequences of resistance variation when the voltage bias is maintained constant. The 1340 nm wavelength thermal laser used in OBIRCH is capable of altering the electrical nature of defects, in particular resistive defects [1]. In general, there are two operating modes, namely static and dynamic, or also known as tester-based as shown in Fig. 1. For static mode, both continuous [2] and pulsed laser are commonly used. The latter is usually implemented in conjunction with a lock-in amplifier to improve signal-to-noise ratio (SNR) [3]. Dynamic fault isolation (FI) which typically involves running a series of test cycles to sensitize logic circuits in order to access the defect is a complementary approach to static FI.
Unlike static OBIRCH, significant fluctuations in supply current due to varying chip current consumption at different test cycles pose a challenge in the deployment of dynamic OBIRCH (D-OBIRCH) [3]. It presents as noise in the signal image. In addition, Fig. 2(a) and (b) depicts two system setup configurations that represent static and tester-based OBIRCH respectively. As shown in Fig. 2(a), static power-up involves a single ground path while Fig. 2(b) shows an additional ground path since the tester shares the same ground connection as the amplifier module (part of the scanning optical microscope, SOM). As a result, a ground loop is formed. If GND1 and GND2 are not at the same potential, high fluctuation ground noises could be generated and this contributes to a secondary noise component in the deployment of dynamic OBIRCH.
To mitigate system noise, the test clock can be frozen temporarily to induce a pseudo static state in the chip. Although this reduces the native noise fluctuation as a result of chip consumption, it does not resolve the ground loop noise. To manage the latter, a slight modulation on top of the VDD voltage level [4] (at a noise-free frequency range) and detecting the signal using a lock-in amplifier can be employed. Besides the pre-requisite of additional hardware, this approach can only be achieved if the specific test cycle that sensitizes the defective net is known. Otherwise, it becomes an arduous task to analyze each cycle iteratively. It is still more efficient to loop the entire test pattern in global electrical fault isolation (EFI). This is the primary motivation behind this work.
We improvise the dynamic OBIRCH setup based on variation mapping for both pseudo static (freeze clock) and test looping (free running clock) application mode. The next section describes 3 proposed methods: 1 freeze clock mode based on variation mapping, 2 free running clock mode techniques based on Shapiro-Wilk index, and Δ Shapiro-Wilk index. Experimental results are provided as proof-of-concept before the last section concludes.
Section snippets
Effective resistance variation mapping
We introduce a configuration of an OBIRCH set up on an automated tester as shown in Fig. 3. The chip is powered up and held at a particular test cycle of interest by holding the tester clock. The tester built-in parametric measurement unit (PMU) samples the supply current for each pixel as laser from the scanning optical microscope rasters and stores the current data in a log. The effective resistance signal image can be calculated based on the constant voltage bias. By synchronizing the tester
Experimental results
Three methods namely, Type A, B and C have been proposed in the last section. In this section, 5 case studies will be presented as an illustration.
Conclusion
The greatest challenge in the application of dynamic OBIRCH for global defect localization lies in the handling of noise that may arise from two main sources: system setup noise and intrinsic device current fluctuations. The latter can be mitigated should the exact test cycle of interest be known which the norm is. This work proposes three variants of resistance variation mapping techniques to overcome the challenges. The first approach involves the generation of an induced resistance variation
CRediT authorship contribution statement
MH Thor: Conceptualization, Methodology, Data collection and curation, Investigation, Validation and Writing.
SH Goh: Methodology, Supervision, Writing, Reviewing and Editing.
BL Yeoh: Supervision and Data collection.
YH Chan: Software and test template preparation.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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