Social learning discrete Particle Swarm Optimization based two-stage X-routing for IC design under Intelligent Edge Computing architecture☆
Graphical abstract
Introduction
In the world of the Internet-of-Things (IoT), a new concept is gaining popularity — Intelligent Edge Computing (IEC). The “edge” refers to the ability of every edge device in the Internet-of-Things to process data, rather than simply storing data in the cloud. IEC is a new computing technique, and one of its core features is real-time decision making and rapid response. Therefore, IC design under Intelligent Edge Computing architecture pays more attention to low delay. [1] finds that deep learning can solve the complex problems in emerging cloud computing architecture more efficiently because of its processing capacity for large-scale data sets. And the deep reinforcement learning method is combined with vehicle edge computing to solve the joint optimization problem of task scheduling and resource allocation in [2]. [3] investigates the neural morphological memory structures that can be used in edge computing in order to improve the ability of data processing under lower power requirements and adapt to the increasing data scale. In [4], the existing edge computing systems are comprehensively summarized, and the technology of deploying deep learning model at the edge is proposed. In Very Large Scale Integration (VLSI) routing, wirelength is the most important index that affects the final delay of the chip. And Steiner Minimum Tree (SMT) is the best connection model in VLSI routing with wirelength as the optimization goal. The SMT problem is to find a routing tree with the least cost to connect all given pins by introducing additional points (Steiner points). Therefore, the SMT construction is a most important issue in VLSI routing.
With the continuous progress and development of VLSI manufacturing processes, the interconnect wire effect has gradually become an important factor affecting the delay of the chip, which finally affects the chip performance. Most current researches on routing algorithms are based on the Manhattan structure [5], [6], [7], [8], [9], but these algorithms are limited in the ability to optimize the length of routing tree. The routing model based on Manhattan structure requires that the way of routing between pins can only be horizontal or vertical, which makes it more difficult to get high quality wirelength optimization results in the IC design. Therefore, the research focus of scholars has gradually shifted to non-Manhattan structure that can make full use of routing resources [10], thus it can better satisfy the demand of low delay of IC design under Intelligent Edge Computing architecture.
In recent years, Soft Computing (SC) has received great attention in the field of optimization. It simulates the biochemical processes of intelligent systems in nature, and can obtain low-cost solutions and robustness. By introducing hybrid soft computing technology, [11] reduces the impact of rapid data growth on the efficiency and accuracy of image and video retrieval process. [12] optimizes 3D IC interconnect delay problem with fixed shape constraints in two stages. In [13], aiming at an approximate optimal travel route, an optimal picking plan is constructed by random transposition to obtain a better solution. And the influence of parameter selection and implementation technology on Genetic Algorithm (GA) is investigated to further improve the performance of GA in [14]. Besides, Swarm Intelligence (SI) based algorithms have been gradually incorporated into SC because of their characteristics of both intelligent decision making and evolutionary computing. [15] and [16] made a relevant research on the application of several classic SI techniques in VLSI routing, and pointed out that Particle Swarm Optimization (PSO) with the simplicity and excellent search ability has obvious advantages in optimizing routing algorithms, especially improving the quality of Steiner tree solution. However, since the traditional PSO technique finishes the social learning of particles by learning only from the global best particle, which makes it difficult to jump out once the algorithm falls into a local extreme.
Therefore, this paper is dedicated to improving the PSO technique to make the algorithm well balance exploitation and exploration capabilities, so as to obtain high-performance routing results which are more suitable for low delay requirement in IC design under Intelligent Edge Computing architecture. This paper proposes a Two-Stage X-routing Steiner Minimum tree (TS-XSMT) construction algorithm based on Social Learning Discrete Particle Swarm Optimization (SLDPSO), consisting of the following two stages.
At this stage, the algorithm searches for a satisfactory X-routing Steiner Tree (XST) with a short wirelength through the PSO technique, which is a classical and efficient intelligent technique in Soft Computing. First, the edge-vertex encoding strategy and an effective fitness function are designed to make the algorithm better solve the discrete XSMT construction problem. Second, chaotic descending inertia weight is used to enhance the global search ability of the algorithm. Then a new social learning strategy is proposed to change the single learning method that the particle learns only from individual historically optimal particle (pbest) or the optimal particle of the swarm (gbest) in each iteration. And with the novel social learning strategy, the particles are continuously changed in each iteration through the learning example pool, which can enhance the diversity of population evolution. Finally, mutation and crossover operators are integrated into the particle update formula to realize the discretization of PSO, thereby constructing the Steiner tree with shortest length.
At this stage, an effective strategy based on local topology optimization is used to reduce the length of XST. By continuously adjusting the local optimal structure near each pin, the length of the routing tree is further optimized to obtain the final XSMT. The proposed algorithm can obtain the best routing solution with shortest wirelength compared with similar work, which is helpful to further reduce the delay and satisfy the high-performance requirement of IC design under Intelligent Edge Computing architecture.
The rest of this paper is organized as follows. Section 2 presents the preliminaries. And Section 3 describes the design ideas and implementation of the TS-XSMT algorithm in detail, including SLDPSO Searching and Wirelength Reduction. In order to verify the good performance of the proposed TS-XSMT, the experimental comparisons of related strategies and algorithms are given in Section 4. Finally, Section 5 concludes this paper. In order to make it easier for reading, Table 1 lists the proper nouns and related technologies mentioned in this paper.
Section snippets
X-routing
X-routing is a non-Manhattan structure that has been studied by many scholars because it has more routing directions than the traditional Manhattan structure. In addition to horizontal and vertical directions, the X-routing tree can lay out 45° and 135° wires to make full use of routing resources and finally achieve superior topologies.
In order to obtain a shorter wirelength than the Manhattan structure, scholars used precise algorithm [17] to construct a non-Manhattan structure routing tree
Problem formulation
The SMT construction based on X-routing is more complicated than the traditional RSMT problem. Traditional RSMT has only horizontal and vertical routing directions. While the X-routing belongs to non-Manhattan structure, it can also route in and directions in addition to the horizontal and vertical directions. The XSMT problem can be described as follows: Given a set of pins , each pin is represented by a coordinate pair . Then connect all pins in through some
Details of SLDPSO based Two-Stage X-routing for IC design under IEC architecture
The Two-Stage XSMT construction algorithm proposed in this paper first finds a satisfactory XST with a short wirelength through SLDPSO Searching. At this stage, the chaotic descending mutation strategy and a novel social learning strategy combined with the crossover operator are added to the PSO to improve the search efficiency. And it can balance the exploitation and exploration capabilities of the algorithm. Then adjust the local optimal structure of the Steiner tree through Wirelength
Experimental results
In order to verify the performance and effectiveness of the proposed algorithm and related strategies in this paper, experiments are performed on the benchmark circuit suite [57], and detailed comparison results are given in this section. The scale of this benchmark includes nets with pins from 8 to 1000. The parameter settings in this paper are consistent with the literature [50], that is, chaotically decreases from 0.95 to 0.4, decreases linearly from 0.82 to 0.5, and increases
Conclusion
Intelligent Edge Computing plays an important role in the application of Internet of Things, and one of its core features is real-time decision making. Therefore, IC design under Intelligent Edge Computing should pay more attention to low delay. And in VLSI routing, wirelength is one of the most important indexes affecting the final delay of the chip. Therefore, aiming at SMT routing model and utilizing the X-routing with better wirelength optimization ability, this paper proposes a two-step
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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This work was supported in part by National Natural Science Foundation of China (No. 61877010, 11501114), Natural Science Foundation of Fujian Province, China (2019J01243).