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OEE improvement by pogo pin defect detection in wafer probing process

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Abstract

It is usually very difficult to find the causes of low yield performance in semiconductor manufacturing. In a typical wafer probing process, when the yield is low, engineers are required to examine both the equipment and the products to clarify if the low yield performance could be contributed by the testing conditions or the products. No matter which were the main cause, the time-consuming trouble-shooting process itself demanded resources thus the overall equipment effectiveness (OEE) is also damaged. This paper dealt with the trouble shooting data of wafer probing process. By examining the main factors that may affect the yield and equipment downtime in the wafer probing process, this study conducted various experiments to explore the relationship between yield and various wafer probing settings such as cleaning sheet size, probing overdrive, touch down time, and contact resistance. As a results, the optimal conditions of the main factors for improving yield and OEE are presented.

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Acknowledgements

The authors have no conflict of interest to declare. All co-authors have seen and agree with the contents of the manuscript and there is no financial interest to report. We certify that the submission is original work and is not under review at any other publication.

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Authors and Affiliations

  1. Department of Industrial Engineering and Management, National Chiao Tung University, 1001 University Road, Hsinchu, 300, Taiwan, ROC

    Woonyoung Yeo, Yung-Chia Chang & Wayne Liu

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  1. Woonyoung Yeo
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  2. Yung-Chia Chang
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  3. Wayne Liu
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Correspondence to Woonyoung Yeo.

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Yeo, W., Chang, YC. & Liu, W. OEE improvement by pogo pin defect detection in wafer probing process. Microsyst Technol 27, 3111–3123 (2021). https://doi.org/10.1007/s00542-020-05189-7

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  • DOI: https://doi.org/10.1007/s00542-020-05189-7

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