Design and experimentation of VDTA based oscillators using commercially available integrated circuits

Abstract

With the focus of employing single Voltage Differencing Transconductance Amplifier (VDTA) in designing of electronically tunable oscillators, three configurations have been proposed in this manuscript. Each configuration enjoys an efficient integrated circuit implementation due to use of grounded capacitors. Unambiguous and independent control of its condition and frequency of oscillation is an additional feature which is available in all the configurations along with the quadrature outputs in voltage mode. The designed configurations have been tested both through simulation and experimental setup employing a newly proposed hardware arrangement of VDTA designed using off the shelf IC, i.e., OPA860. Moreover, the oscillators have also been experimentally justified with already available hardware realization of VDTA. Experimentation results generated using two different ICs, with two different hardware setups, have been tabulated so as to provide an illustrative study of the performances of oscillators.

Appendix

In order to verify the workability of all designed oscillators, Cadence ORCAD PSPICE simulation software has been used. This section includes all the simulated curves which have been generated for justifying the proposed ideas, in current mode of operation. The CMOS version of VDTA employed during software analysis has been taken from [30]. With the use of 0.35 µm TSMC process parameters, and supply voltages of ± 2 V, all the graphs have been obtained. The aspect ratios of transistors are stated in Table 5. The supply currents, i.e., I_BS and I_BF, are responsible for controlling the trans-conductance values of the employed device.

Table 5 Aspect ratios of transistors utilized in CMOS version of VDTA

Validating the performance of proposed oscillators 1, shown in Table 1, initially all basic responses have been provided. Table

Table 6 Simulated curves obtained through CMOS structure VDTA

6 includes the transient response of designed oscillator which is operating at 1.01 MHz of frequency, ideally. For achieving this frequency, a bias current of 20 µA has been supplied to the circuit. Correspondingly, the value of transconductances, i.e., g₂ and g₃, is 266.3 µA/V. The passive component values have been adjusted to C₁ = C₂ = 42 pF, and R₁ which is used for controlling the condition of oscillation has been kept as 3.8 kΩ. Steady state response has been obtained by focusing on few oscillations of the transient response. This analysis makes it evident that the proposed idea is capable of producing smooth sinusoidal wave, with quadrature results. The presence of harmonics at frequencies other than frequency of oscillation, along with amplitude attained at all frequencies, is depicted by Fast Fourier analysis (FFT). All these basic responses indicate that the simulated FO is 998 kHz, thus giving an error percentage of 1.1.

Similar set of analysis has been performed for designed oscillator 2, provided in Table 2. In this case, the ideal FO has been selected as 1 MHz, for which the passive element values have been taken as C₁ = C₂ = 60 pF and R₁ = 2.7 kΩ, which is altered for adjusting CO. The transconductance factors, i.e., g₂ and g₃, have been kept as 380 µA/V, according to which the supplied bias current is 40 µA.

All the related simulation graphs have been presented in Table 6. The transient response shows the attainment of steady oscillations, whereas the steady state graph provides a closer look into the nature of produced waveform. As in the above scenario, the presence of harmonics at different frequencies is depicted in FFT response. From all these curves, the actual simulated FO was generated as 987 kHz, producing an error of 1.3%.

By keeping the ideal FO, of designed oscillator 3, as 1 MHz, the working of this proposed configuration has been tested. Here, the passive elements were kept as C₁ = C₂ = 80 pF and R₃ = 3 kΩ. A supply of bias current of amplitude 160 µA resulted in the value of transconductances, i.e., g₁ and g₂, being 763 µA/V. The transient response which indicates the rise of oscillations obtained as output from the designed circuit, is provided in Table 2. Along with it steady state response and FFT analysis have also been included. These responses depict the exact nature of curves generated by the configuration and attainment of harmonics in a range of frequencies, respectively. The simulated FO, in this case, is 955 kHz, thus providing an error percentage of 4.5.

In order to summarize the available oscillator networks which have been verified using CMOS structure of active device, a brief literature survey has been provided in Table 7. The table shows the technologies which have been earlier utilized in simulating oscillators, along with all expressed features.

Table 7 Literature Survey of oscillators simulated using CMOS structures