Abstract
A physics-based compact model for halo doped Silicon Nanowire Transistor with Schottky-barrier (SB) contact at the source/drain (S/D) junctions is developedconsidering the quasi-2D surface-potential solution. The halo implant is considered only at the source side to avoid hot electron effects in the high field drain region. The surface potential and electric field expressions are derived using a systematic approach. The impact of a single halo at the source is analyzed using the energy band model. The analysis shows that the halo increases the electron energy at the source side and suppresses the short channel effects. Moreover, high doping of halo decreases the tunneling barrier width, thereby increasing the ON-state current. Physics-based modeling of the surface potential at the halo boundary has ensured that the model preserves accuracy and continuity.
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References
Huang X, Lee WC, Kuo C, Hisamoto D, Chang L, Kedzierski EA, Takeuchi H, Choi YK, Asano K, Subramanian V, King TJ, Bokor J, Hu C (1999) Sub 50-om FinFET: PMOS, in IEDM Tech. Dig., 67–70
Jimenez D, Iniguez B, Sune J, Marsal LF, Parrares J, Roig J, Flores D (2004) Continuous analytical I–V model for surrounding-gate MOSFETs. IEEE Electron Device Lett 25(8):571–573
Hiroshi I, Kenji N, Kenji S, Jun-ichi I, Atsushi O, Keisaku Y, Kenji O, Kuniyuki K, Parhat A (2011) Si nanowire FET and its modeling. Science China 54(5):1004–1011
Chen Z, Zhou X, Zhu G, Lin S (2010) Interface-trap modeling for silicon-nanowire MOSFETs, 2010 IEEE International Reliability Physics Symposium, Anaheim, CA, 977–980
Larson JM, Snyder JP (May 2006) Overview and status of metal S/D Schottky barrier MOSFET technology. IEEE Trans Electron Dev 53(5):1048–1058
Taur Y, Ning TH (2009) Fundamentals of Modern VLSI Devices, Cambridge:Cambridge University Press, second edition, 196
Schwarz M, Kloes A (2016) Analysis and performance study of III–V Schottky barrier double-gate MOSFETs using a 2-D analytical model. in IEEE Transactions on Electron Devices 63(7):2757–2763
Iwai H, Natori K, Shiraishi K, Iwata JI, Oshiyama A, Yamada K, Ohmori K, Kakushima K, Ahmet P (2011) Si nanowire FET and its modeling. Sci China Inf Sci 54:1004–1011
Hamid HA, Iniguez B, Roig J (2007) Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all around-based MOSFETs. IEEE Trans Electron Dev 54:572
Wong H (2018) Compact Modeling and Short-Channel Effects of Nanowire MOS Transistors (Invited), 2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), Beijing, China, 7–10
Li ZC (2008) Performance and analytical modeling of halo-doped surrounding gate MOSFETs. Chinese Phys B 17:4312
Zhu GJ, Zhou X, Chin YK, Pey KL, Zhang J, See GH, Lin SH, Yan Y, Chen Z (2010) Subcircuit Compact Model for Dopant-Segregated Schottky Gate-All-Around Si-Nanowire MOSFETs. IEEE Trans. Electron Dev 57(4):772–781
Zhu GJ, Zhou X, Lee TS, Ang LK, See GH, Lin SH, Chin YK, Pey KL (2009) A compact model for undoped silicon nanowire MOSFETs with Schottky barrier source/drain. IEEE TransElectron Dev 56(5):1100–1109
Mohankumar N, Syamal B, Sarkar CK (2010) Influence of channel and gate engineering on the analog and RF performance of DG MOSFETs. in IEEE Trans Electron Dev 57(4):820–826
Mohankumar N, Syamal B, Sarkar CK (2009) Investigation of Novel Attributes of Single Halo Dual-Material Double Gate MOSFETs for Analog/RF Applications, published in Micro Electronics Reliability, 49, 12, 1491–1497
Zhu GJ, See GH, Lin SH, Zhou X (2008) Ground-referenced model for three-terminal symmetric double-gate MOSFETs with source/drain symmetry. IEEE Trans. Electron Dev 55(9):2526–2530
Vishnoi R, Kumar MJ (2014) A Pseudo 2D-analytical Model of Dual Material Gate All-Around Nanowire Tunneling FET. IEEE Trans. on Electron Devices 61:2264–2270
Syamal B, Bose C, Sarkar CK, Mohankumar N (2010) Effect of Single HALO Doped Channel in Tunnel FETs: A 2-D Modeling Study, IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)
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Mishra, G.S., Mohankumar, N., Mahesh, V. et al. Compact Modeling of Schottky Gate-all-around Silicon Nanowire Transistors with Halo Doping. Silicon 14, 1455–1462 (2022). https://doi.org/10.1007/s12633-020-00936-x
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DOI: https://doi.org/10.1007/s12633-020-00936-x