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A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation

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Abstract

The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of the image in terms of peak signal-to-noise ratio (PSNR) and structural similarity index matrix (SSIM). In addition, different types of RLGs are used to perform the encryption and decryption of the images. A random number is generated using the Lorenz chaotic system (LCS) that contains three different stages and each stage is developed using arithmetic blocks. Here, an effective key value is generated from the input image values by connecting the LCS’s output with the heterogeneous key generation (HKG) module. The inverse IWT (IIWT) technique is used to retrieve the original data during execution of decryption operation. Application specific integrated circuit and field-programmable gate array (FPGA) performances are calculated for reversible logic cryptographic design (RLCD) IWT-HKG architecture. The results showed that it has achieved better performance compared to conventional methods. Moreover, security analyses such as avalanche effect, side channel attack and session key agreement are performed for the RLCD-IWT-HKG method. The RLCD-IWT-HKG method has achieved 89 LUTs, 52 flip flops and 31 slices for the Virtex 6 FPGA device. After retrieving the decrypted images, values of PSNR and SSIM are evaluated as 39.90 dB and 0.6874, respectively.

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Data Availability

The datasets generated during the current study are not publicly available due to the usage of real-time images. In this research work, we have captured a real-time dataset using a DSLR camera. But, the real-time datasets are available from the corresponding author on reasonable request.

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This study was not funded by any organization.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore, Tamil Nadu, India

    K. Saranya

  2. Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, Coimbatore, Tamil Nadu, India

    K. N. Vijeyakumar

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  1. K. Saranya
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  2. K. N. Vijeyakumar
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Correspondence to K. Saranya.

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Saranya, K., Vijeyakumar, K. A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation. Circuits Syst Signal Process 40, 3836–3865 (2021). https://doi.org/10.1007/s00034-021-01649-1

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