Skip to main content
SpringerLink
Log in

A New Z-Shaped Gate Line Tunnel FET with Improved Electrostatic Performance

  • Research Paper
  • Published:
Iranian Journal of Science and Technology, Transactions of Electrical Engineering Aims and scope Submit manuscript

Abstract

In this paper, we simulated a new line tunnel field-effect transistor (TFET) with a Z-shaped gate. The proposed Z-TFET generates vertical tunneling due to the presence of the front gate over the entire source region. This generates faster tunneling between the source and the channel region, providing a 3-decade improvement in drain current compared to conventional DG-TFET. The ambipolar current is also improved by 1-decade with a subthreshold swing (SS) of 40 mV/decade (reduces by 18%). Further optimization of the front and back gate is performed to investigate its impact on the analog performance of Z-TFET. The simulated results exhibit improvement in ambipolar current, reduction in OFF current by optimizing the back-gate length. This simulation work is performed in the presence of field-induced quantum confinement using the TCAD device simulator. Additional reliability issue of the structure in the presence of the interface trap charge at the semiconductor-oxide interface is properly investigated. The effect of trap charge density (Nf) and capture cross-section (σ) variation on the transfer characteristics and average SS has been examined. The proposed device can provide a higher ION/IOFF of 1013 and ION/IAMB of 107.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  • Acharya A, Solanki AB, Glass S, Zhao QT, Anand B (2019) Impact of gate-source overlap on the device/circuit analog performance of line TFETs. IEEE Trans Electron Devices 66:4081–4086

    Article  Google Scholar 

  • Anvarifard MK (2019) A nanoscale-modified junctionless with considerable progress on the electrical and thermal issue. Int J Numer Model: Electron Netw Devices 32:1–15

    Article  Google Scholar 

  • Anvarifard MK, Orouji AA (2019) Enhancement of a Nanoscale Novel Esaki Tunneling Diode Source TFET (ETDS-TFET) for low-voltage operations. Silicon 11:2547–2556

    Article  Google Scholar 

  • Anvarifard MK, Ramezani Z, Amiri IS, Nejad AM (2020) A Nanoscale-Modified band energy junctionless transistor with considerable progress on the electrical and frequency issue. Mater Sci Semicond Process 107:104849

    Article  Google Scholar 

  • Avci UE, Rios R, Kuhn K, Young IA (2011) Comparison of performance switching energy and process variations for the TFET and MOSFET in logic. Proceedings of the Very Large Scale Integration (VLSI) Technology Symposium, pp 124–125

  • Baravelli E, Gnani E, Gnudi A, Reggiani S, Baccarani G (2014) TFET inverters with n-/p-devices on the same technology platform for low-voltage/low-power applications. IEEE Trans Electron Devices 61:473–478

    Article  Google Scholar 

  • Barboni L, Siniscalchi M, Rodriguez BS (2015) TFET-based circuit design using the transconductance generation efficiency gm/Id method. Electron Device Soc 3:208–216

    Article  Google Scholar 

  • Bernstein K, Cavin RK, Porod W, Seabaugh A, Welser J (2010) Device and architectures outlook for beyond CMOS switches. Proc IEEE 98:2169–2184

    Article  Google Scholar 

  • Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54:1725–1733

    Article  Google Scholar 

  • Bousari N, Anvarifard M, Haji-Nasiri S (2019) Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering. Int J Electron Commun (AEÜ) 108:226–234

    Article  Google Scholar 

  • Chiang T (2011) A compact model for threshold voltage of surrounding-gate MOSFETs with localized interface trapped charges. IEEE Trans Electron Devices 58:567–571

    Article  Google Scholar 

  • Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28:743–745

    Article  Google Scholar 

  • Dash S, Jena S, Mishra GP (2016) A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping. Superlattices Microstruct 97:231–241

    Article  Google Scholar 

  • Der Agopian PG, Martino JA, Vandooren A, Rooyackers R, Simoen E, Thean A, Claeys C (2017) Study of line-TFET analog performance comparing with other TFET and MOSFET architectures. Solid-State Electron 128:43–47

    Article  Google Scholar 

  • Huang XY, Jiao GF, Cao W, Huang D, Yu HY, Chen ZX, Singh N, Lo GQ, Kwong DL, Li MF (2010) Effect of interface-traps and oxide-charge on drain current degradation in tunneling field-effect transistors. IEEE Electron Device Lett 31:779–781

    Article  Google Scholar 

  • Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nature 479:329–337

    Article  Google Scholar 

  • Khan A, Loan SA (2020) Metal drain double-gate tunnel field effect transistor with underlap: design and simulation. Silicon. https://doi.org/10.1007/s12633-020-00528-9

    Article  Google Scholar 

  • Kim SH, Kam H, Hu C, Liu TJK (2009) Germanium-source tunnel field effect transistors with record high ION/IOFF. In: Proceedings of the very large scale integr. (VLSI) technology symposium, pp 178–179

  • Knoch J, Appenzeller J (2010) Modeling of high-performance p-type III–V heterojunction tunnel FETs. IEEE Electron Device Lett 31:305–307

    Article  Google Scholar 

  • Krishnamohan T, Kim D, Raghunathan S, Saraswat K (2008) Doublegate strained-ge heterostructure tunneling FET (TFET) with record high drive currents and <<60mV/dec subthreshold slope. In: Proceedings of the IEEE international electron devices meeting, pp 1–3

  • Lu Y et al (2012) Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned. IEEE Electron Device Lett 33:655–657

    Article  Google Scholar 

  • Mitra SK, Bhowmick B (2019) Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET. Microelectron Reliab 94:1–12

    Article  Google Scholar 

  • Musalgaonkar G, Sahay S, Saxena RS, Kumar MJ (2019) A line tunneling field-effect transistor based on misaligned Core–Shell gate architecture in emerging nanotube FETs. IEEE Trans Electron Devices 66:2809–2816

    Article  Google Scholar 

  • Narang R, Saxena M, Gupta RS, Gupta M (2012) Assessment of Ambipolar behavior of a tunnel FET and influence of structural modifications. J Semicond Technol Sci 12:482–491

    Article  Google Scholar 

  • Pandey R, Mookerjea S, Datta S (2016) Opportunities and challenges of tunnel FETs. IEEE Trans Circuits Syst I Reg Papers 63:2128–2138

    Article  Google Scholar 

  • Sahoo S, Dash S, Mishra GP (2018) An extensive simulation study of Gaussian drain doped heterojunction double gate TFET. In: IEEE Electron Device Conference 283–287.

  • Schmidt M, Schafer A, Minamisawa RA, Buca D, Trellenkamp S, Hartmann JM, Zhao QT, Mantl S (2014) Line and point tunneling in scaled Si/SiGe heterostructure TFETs. IEEE Electron Device Lett 35:699–701

    Article  Google Scholar 

  • Seabaugh AC, Zhang Q (2010) Low voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98:2095–2110

    Article  Google Scholar 

  • Shabde S, Bhattacharyya A, Kao RS, Muller RS (1988) Analysis of MOSFET degradation due to hot-electron stress in terms of interface-state and fixed-charge generation. Solid State Electron 31:1603–1610

    Article  Google Scholar 

  • Shaikh MRU, Loan SA (2019) Drain-engineered TFET with fully suppressed ambipolarity for high-frequency application. IEEE Trans Electron Devices 66:1628–1634

    Article  Google Scholar 

  • Singh AK, Tripathy MR, Chander S, Baral K, Singh PK, Jit S (2020) Simulation study and comparative analysis of some TFET Structures with a Novel Partial-Ground-Plane (PGP) based TFET on SELBOX structure. Silicon 12:2345–2354

    Article  Google Scholar 

  • Skotnicki T, Hutchby JA, King TJ, Wong HSP, Buf F (2005) The road to the end of CMOS scaling. IEEE Circuits Devices Mag 21:16–26

    Article  Google Scholar 

  • Smets Q et al (2014) Impact of field-induced quantum confinement on the onset of tunneling field-effect transistors: experimental verification. Appl Phys Lett 105:203507-1–203514

    Article  Google Scholar 

  • Synopsys Inc (2014) Sentaurus device. Synopsys Inc, Mountain View

    Google Scholar 

  • Vandenberghe WG, Sorée B, Magnus W, Groeseneken G, Fischetti MV (2011) Impact of field-induced quantum confinement in tunneling field-effect devices. Appl Phys Lett 98:143503-1–143513

    Article  Google Scholar 

  • Venkatesh P, Nigam K, Pandey S, Sharma D, Kondekar PN (2017) Impact of interface trap charges on performance of electrically doped tunnel FET with heterogeneous gate dielectric. IEEE Trans Device Mater Reliab 17:245–252

    Article  Google Scholar 

  • Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G (2008) Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization. J Appl Phys 104:064514-1-064514–10

    Article  Google Scholar 

  • Walke AM et al (2013) Part I: Impact of field-induced quantum confinement on the subthreshold swing behavior of line TFETs. IEEE Trans Electron Devices 60:4057–4064

    Article  Google Scholar 

  • Walke AM, Vandooren A, Rooyackers R, Leonelli D, Hikavyy A, Loo R, Verhulst AS, Kao KH, Huyghebaert C, Groeseneken G, Rao VR, Bhuwalka KK, Heyns MM (2014) Fabrication and analysis of a Si/Si0.55Ge0.45 heterojunction line tunnel FET. IEEE Trans Electron Devices 61:707–715

    Article  Google Scholar 

  • Wang H, Han G, Jiang X, Liu Y, Zhang J, Hao Y (2019b) Improved performance in GeSn/SiGeSn TFET by hetero-line architecture with staggered tunneling junction. IEEE Trans Electron Devices 66:1985–1989

    Article  Google Scholar 

  • Wang PF, Hilsenbeck K, Nirschl Th, Oswald M, Stepper Ch, Weis M, Schmitt-Landsiedel D, Hansch W (2004) Complementary tunneling transistor for low power application. Solid-State Electron 48:2281–2286

    Article  Google Scholar 

  • Wang X, Tang Z, Cao L, Li J, Liu Y (2019a) Gate field plate structure for subthreshold swing improvement of Si line-tunneling FETs. IEEE Access 7:100675–100683

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Siksha ‘O’ Anusandhan (Deemed to be University), Bhubaneswar, Odisha, India

    Sasmita Sahoo & Sidhartha Dash

  2. Department of Electronics and Telecommunication Engineering, SRM Institute of Science and Technology, Chennai, Tamil Nadu, India

    Soumya Ranjan Routray

  3. Department of Electronics and Telecommunication Engineering, National Institute of Technology Raipur, Raipur, India

    Guru Prasad Mishra

Authors
  1. Sasmita Sahoo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sidhartha Dash
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Soumya Ranjan Routray
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Guru Prasad Mishra
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Sidhartha Dash.

Ethics declarations

Conflict of interest

The author declares that he has no conflict of interest.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sahoo, S., Dash, S., Routray, S.R. et al. A New Z-Shaped Gate Line Tunnel FET with Improved Electrostatic Performance. Iran J Sci Technol Trans Electr Eng 45, 1037–1050 (2021). https://doi.org/10.1007/s40998-020-00400-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s40998-020-00400-x

Keywords

Search

Navigation