Skip to main content
Log in

Nanowire Array-based MOSFET for Future CMOS Technology to Attain the Ultimate Scaling Limit

  • Original Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

Silicon nanowire (SiNW) structures are the essential foundations of the next generation highly efficient and lowcost electronic devices because of their specific chemical, optical, and electrical properties. In recent decades, the production of pure Si NW arrays with the ability to tune the wire density and dimensions has been intensively studied. This paper demonstrates the performance of silicon nanowire (Si NW) array based cylindrical gate all around (GAA) MOSFET using quantum transport model in lower technology nodes. With an improvement in drain current and lower value of threshold voltage, the proposed structure is proving itself as one of the leaders in GAA MOSFET family. Again the study includes the effect of variation in gate voltage on the electrostatic potential of individual nanowires and the potential developed at the channel-source/drain interface. The improved ON current with superior electrostatic integrity due to silicon pillars is showing the possibility of this device towards future development in CMOS technology. Finally, the article includes the integration of nMOS and pMOS to realize the CMOS inverter for high speed and noise immune characteristics.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

Data Availability

The authors confirm that the data supporting the findings of this study are available within the article, its supplementary materials or below mentioned references.

References

  1. Auth CP, Plummer JD (1997) Scaling theory for cylindrical, fully depleted, surrounding gate MOSFETs. IEEE Electron Device Lett 18:74

    Article  Google Scholar 

  2. Chiang TK (2005) A scaling theory for fully-depleted, surrounding-gate MOSFET’s: including effective conducting path effect. Microelectron Eng 77:2175

    Article  Google Scholar 

  3. Cao H, Li X, Zhou B, Chen T, Shi T, Zheng J, Liu G, Wang Y (2017) On-demand fabrication of Si/SiO2 nanowire arrays by nanosphere lithography and subsequent thermal oxidation. Nanoscale Res Lett 12:170

    Article  Google Scholar 

  4. Kranti A, Haldar S, Gupta RS (2001) Analytical model for threshold voltage and I-V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET. Microelectron Eng 56:241

    Article  CAS  Google Scholar 

  5. Jimenez D (2004) Continuous analytic I–V model for surrounding-gate MOSFETs. IEEE Electron Device Lett 25:571

    Article  Google Scholar 

  6. Liu F, He J, Zhang L, Zhang J, Hu J, Ma C, Chan M (2008) A charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body. IEEE Trans Electron Devices 55:2187

    Article  CAS  Google Scholar 

  7. Chiang TK (2009) A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs. Solid-State Electronics 53:490

    Article  CAS  Google Scholar 

  8. Taur Y, Buchanan DA, Chen W, Frank DJ, Ismail KE, Lo SH, Sai-Halasz GA, Viswanathan RG, Wann HJC, Wind SJ, Wong HS (1997) CMOS scaling into the nanometer regime. Proc. IEEE 85:486

  9. Nowak EJ (2002) Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J Res Dev 46:160

    Article  Google Scholar 

  10. Haensch W, Nowak EJ, Dennard RH, Solomon PM, Bryant A, Dokumaci OH, Kumar A, Wang X, Johnson JB, Fischetti MV (2006) Silicon CMOS devices beyond scaling. IBM J Res Dev 50:339

    Article  CAS  Google Scholar 

  11. Kuhn K (2012) Considerations for ultimate CMOS scaling. IEEE Trans Electron Devices 59:1813

    Article  CAS  Google Scholar 

  12. Pradhan KP, Saha SK, Sahu PK, Priyanka (2017) Impact of fin height and fin angle variation on the performance matrix of hybrid FinFETs. IEEE Trans Electron Devices 64:52

    Article  CAS  Google Scholar 

  13. Pradhan KP, Priyanka M, Rao PK, Sahu SK, Mohapatra, (2015) Analysis of symmetric high-k spacer (SHS) trigate wavy FinFET: a novel device. INDICON, New Delhi, p 1

    Google Scholar 

  14. Mohapatra SK, Pradhan KP, Sahu PK (2014) Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET. FU Elec Energ 27:613

    Google Scholar 

  15. Das SK, Swain SK, Biswal SM, Nayak D, Nanda U, Baral B, Tripathy D (2019) Effect of High-K spacer on the performance of gate-stack uniformly doped DG-MOSFET. 2019 Devices for Integrated Circuit (DevIC), pp. 365–369

  16. Keerthana P, Babu PP, Babu TA, Jena B (2020) Performance analysis of GAA MOSFET for lower technology nodes. J Eng Sci Technol Rev 13:39

    Article  Google Scholar 

  17. Egard M, Johansson S, Johansson AC, Persson KM, Dey AW, Borg BM, Thelander C, Wernersson LE, Lind E (2010) Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz. Nano Lett 10:809

    Article  CAS  Google Scholar 

  18. Wang B, Stelzner T, Dirawi R, Assad O, Shehada N, Christiansen S, Haick H (2012) Field-effect transistors based on silicon nanowire arrays: effect of the good and the bad silicon nanowires. ACS Appl Mater Interfaces 4:84251

    Google Scholar 

  19. Chiang TK (2006) A New Two-dimensional analytical model for threshold voltage in undoped surrounding-gate MOSFETs, 2006, 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai pp. 1234–1238

  20. Swain SK, Das SK, Biswal SM, Adak S, Nanda U, Saha AA, Nayak D, Baral B, Nayak D (2019) Effect of high-K spacer on the performance of non-uniformly doped DG-MOSFET. Devices for Integrated Circuits (DevIC), Kalyani, p 510

    Google Scholar 

  21. He J, Tao Y, Liu F, Feng J (2007 Analytical channel potential solution to the undoped surrounding gate MOSFETs. Solid State Electron 51:802

    Article  CAS  Google Scholar 

  22. Kaur H, Kabra S, Bindra S, Haldar S, Gupta RS (2007) Impact of graded channel (GC) design in fully depletedcylindrical/surrounding gate MOSFET (FD CGT/SGT) forimproved short channel immunity and hot carrier reliability. Solid-State Electronics 51:398

    Article  CAS  Google Scholar 

  23. Liu F, He J, Zhang L, Zhang J, Hu J, Ma C, Chan M (2008) A charge-based model for long-channel cylindrical surrounding-gate MOSFETs from intrinsic channel to heavily doped body. IEEE Trans Electron Devices 55:2187)

  24. Chiang TK (2009) A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs. Solid-State Electronicsvol 53:490

    Article  CAS  Google Scholar 

  25. Li C, Zhuang Y, Han R (2011) Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension. Microelectron J 42:341

  26. Srivastava VM, Yadav KS, Singh G (2011) Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch. Microelectron J 42:1124

  27. Ghosh P, Haldar S, Gupta RS, Gupta M (2012) An analytical drain current model for dual material engineered cylindrical/surrounded gate MOSFET. Microelectron J 43:17

  28. Jena B, Dash S, Routray SR, Mishra GP (2019) Inner-Gate-Engineered GAA MOSFET to enhance the electrostatic integrity. Nano 14:1950128

    Article  CAS  Google Scholar 

  29. Jena B, Dash S, Pradhan KP, Mohapatra SK, Sahu PK, Mishra GP (2015) Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime. Adv Nat Sci Nanosci Nanotechnol 6:035010

  30. Biswal SM, Swain SK, Sahoo JR, Swain AK, Routaray K, Nanda U (2018) A comparative study of junctionless triple-material cylindrical surrounding gate tunnel FET. Microelectronics, Electromagnetics and Telecommunications, Springer Nature, Berlin, 793

  31. Tayal S, Mittal V, Jadav S, Gupta S, Nandi A, Krishnan B (2020) Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective. Cryogenics 108:103087

    Article  CAS  Google Scholar 

  32. Sanjay B, Prasad A, Vora, (2020) Dual material gate engineering to reduce DIBL in cylindrical gate all around Si nanowire MOSFET for 7-nm gate length. Semiconductors 54:1490

    Article  CAS  Google Scholar 

  33. Sentaurus Device User Guide. Synopsys, Inc, Mountain View

  34. Nayak D, Acharya DP, Rout PK, Nanda U (2018) A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array. Solid-State Electron Elsevier 148:43

    Article  CAS  Google Scholar 

  35. Nayak D, Rout PK, Sahu S, Acharya DP, Nanda U, Tripthy D (2020) A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance. Microelectron J 97:104723

    Article  Google Scholar 

Download references

Acknowledgements

The Authors would like to thank School of Electronics Engineering, Vellore Institute of Technology,Vellore, for their support to use Sentaurus TCAD simulator to carry out this simulation.

Author information

Authors and Affiliations

Authors

Contributions

Krutideepa Bhol- Conceptualization, methodology, simulation and investigation, Umakanta Nanda- Validation, original draft preparation, reviewing and editing.

Corresponding author

Correspondence to Umakanta Nanda.

Ethics declarations

This article does not contain any studies with humanparticipants or animals performed by any of the authors.

Conflict of Interest

The authors declare that they have no conflict of interest.

Consent to Participate

All authors freely agreed and gave their consent to participate on thiswork.

Consent for Publication

All authors freely agreed and gave their consent for the publication of this paper.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Bhol, K., Nanda, U. Nanowire Array-based MOSFET for Future CMOS Technology to Attain the Ultimate Scaling Limit. Silicon 14, 1169–1177 (2022). https://doi.org/10.1007/s12633-020-00909-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00909-0

Keywords

Navigation