Skip to main content
Log in

Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors

  • Review Paper
  • Published:
Silicon Aims and scope Submit manuscript

Abstract

As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

Data Availability

The research data of this manuscript will not be available.

References

  1. International technology roadmap for semiconductors (ITRS). (2015)

  2. Sze SM (2008) Semiconductor devices: physics and technology. John wiley & sons, Hoboken

  3. Colinge JP (2008) The new generation of SOI MOSFETs. Rom J Inf Sci Technol 11(1):3–15

    Google Scholar 

  4. Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Dev 36(2):399–402

    Google Scholar 

  5. Sharma SK, Jain A, Raj B (2018) Analysis of triple metal surrounding gate (TM-SG) III–V nanowire MOSFET for photosensing application. Opto-Electronics Rev 26(2):141–148

    Google Scholar 

  6. Kim YB (2010) Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater 11(3):93–105

    Google Scholar 

  7. Bala S, Khosla M (2018) Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design. J Comput Electron 17(4):1528–1535

    Google Scholar 

  8. International Technology Roadmap for Semiconductors (ITRS), 2010 update

  9. Colinge JP (2004) Novel gate concepts for MOS devices. In Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No. 04EX850), pp 45–49

  10. Larson JM, Snyder JP (2006) Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans Electron Dev 53(5):1048–1058

    CAS  Google Scholar 

  11. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229

    CAS  PubMed  Google Scholar 

  12. Kranti A, Yan R, Lee CW et al (2010) Junctionless nanowire transistor (JNT): properties and design guidelines. IEEE Proc European Solid State Device Res Conference 14:357–360

    Google Scholar 

  13. Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Nazarov AN, Doria RT (2010) Reduced electric field in junctionless transistors. Appl Phys Lett 96(7):073510

    Google Scholar 

  14. Colinge JP, Lee CW, Akhavan ND, et al. (2011) Junctionless transistors: physics and properties. In: Nazarov A, Colinge JP, Balestra F, Raskin JP, Gamiz F, Lysenko V (eds) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Springer, Berlin, Heidelberg, pp 187–200

  15. Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP (2010) Performance estimation of junctionless multigate transistors. Solid State Electron 54(2):97–103

    Google Scholar 

  16. Wang Y, Shan C, Dou Z, Wang LG, Cao F (2015) Improved performance of nanoscale junctionless transistor based on gate engineering approach. Microelectron Reliab 55(2):318–325

    CAS  Google Scholar 

  17. Colinge JP, Lee CW, Afzalian A et al (2009) SOI gated resistor: CMOS without junctions. IEEE Int SOI Conference 5:1–2

    Google Scholar 

  18. Colinge JP, Kranti A, Yan R et al (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65:33–37

    Google Scholar 

  19. Skotnicki T, Merckel G, Pedron T (1988) The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Lett 9(3):109–112

    Google Scholar 

  20. Jeon DY, Park SJ, Mouis M, Barraud S, Kim GT, Ghibaudo G (2013) Low-temperature electrical characterization of junctionless transistors. Solid State Electron 80:135–141

    CAS  Google Scholar 

  21. Skotnicki T (2000) Heading for decananometer CMOS-Is navigation among icebergs still a viable strategy?. In 30th IEEE European Solid-State Device Research Conference, Cork, pp 19–33

  22. Shehata N, Gaber AR, Naguib A et al (2015) 3D multi-gate transistors: concept, operation, and fabrication. J Electr Eng 3:1–4

    Google Scholar 

  23. Colinge JP (2014) Multigate transistors: pushing Moore's law to the limit. In IEEE International Conference on Simulation of Semiconductor Processes and Devices, IEEE, Yokohama, pp 313–316

  24. Razavi P, Fagas G, Ferain I et al (2011) Performance investigation of short-channel junctionless multigate transistors. IEEE Ultimate Integrat Silicon 14:1–3

    Google Scholar 

  25. Gundapaneni S, Ganguly S, Kottantharayil A (2011) Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett 32(3):261–263

    CAS  Google Scholar 

  26. Taur Y, Ning TH (2013) Fundamentals of modern VLSI devices. Cambridge University Press, Cambridge

  27. Holtij T, Schwarz M, Kloes A, Iniguez B (2013) Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region. Solid State Electron 90:107–115

    CAS  Google Scholar 

  28. Han MH, Chang CY, Jhan YR, Wu JJ, Chen HB, Cheng YC, Wu YC (2013) Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis. IEEE Electron Device Lett 34(2):157–159

    Google Scholar 

  29. Holtij T, Schwarz M, Kloes A, Iñíguez B (2012) 2D analytical potential modeling of junctionless DG MOSFETs in subthreshold region including proposal for calculating the threshold voltage. In 2012 13th International Conference on Ultimate Integration on Silicon (ULIS), IEEE, Grenoble

  30. Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511

    Google Scholar 

  31. Tai CH, Lin JT, Eng YC, Lin PH (2010) A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer. In 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. IEEE, Shanghai, pp 108–110+

  32. Dehdashti AN, Ferain I, Razavi P et al (2011) Improvement of carrier ballisticity in junctionless nanowire transistors. Appl Phys Lett 98(10):103510

    Google Scholar 

  33. Leung G, Chui CO (2011) Variability of inversion-mode and junctionless FinFETs due to line edge roughness. IEEE Electron Device Lett 32(11):1489–1491

    Google Scholar 

  34. Moon DI, Choi SJ, Duarte JP, Choi YK (2013) Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate. IEEE Trans Electron Devices 60(4):1355–1360

    CAS  Google Scholar 

  35. Jin X, Liu X, Lee JH (2013) Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors. Phys Scr 89(1):015804

    Google Scholar 

  36. Tsormpatzoglou A, Dimitriadis CA, Clerc R, Pananakakis G, Ghibaudo G (2008) Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans Electron Devices 55(9):2512–2516

    Google Scholar 

  37. Chiang TK (2012) A new quasi-2-D threshold voltage model for short-channel junctionless cylindrical surrounding gate (JLCSG) MOSFETs. IEEE Trans Electron Devices 59(11):3127–3129

    Google Scholar 

  38. Li C, Zhuang Y, Di S, Han R (2013) Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans Electron Devices 60(11):3655–3662

    Google Scholar 

  39. Xiao Y, Zhang B, Lou H, Zhang L, Lin X (2016) A compact model of subthreshold current with source/drain depletion effect for the short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans Electron Devices 63(5):2176–2181

    Google Scholar 

  40. Pandey RK, Murali KV et al (2010) Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs. IEEE Trans Electron Devices 57(9):2098–20105

    Google Scholar 

  41. Ananthan H, Bansal A, Roy K (2005) Analysis of drain-to-body band-to-band tunneling in double gate MOSFET. In 2005 IEEE International SOI Conference Proceedings, IEEE, Honolulu, pp 159–160

  42. Gundapaneni S, Bajaj M, Pandey RK, Murali KVRM, Ganguly S, Kottantharayil A (2012) Effect of band-to-band tunneling on junctionless transistors. IEEE Trans Electron Devices 59(4):1023–1029

    CAS  Google Scholar 

  43. Wu M, Jin X, Kwon HI, Chuai R, Liu X, Lee JH (2013) The optimal design of junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling. J Semiconduct Technol Sci 13(3):245–251

    Google Scholar 

  44. Poindexter EH (1989) MOS interface states: overview and physicochemical perspective. Semicond Sci Technol 4(12):961–969

    CAS  Google Scholar 

  45. Trabzon L, Awadelkarim OO (1998) Damage to n-MOSFETs from electrical stress relationship to processing damage and impact on device reliability. Microelectron Reliab 38(4):651–657

    Google Scholar 

  46. Lho YH, Kim KY (2005) Radiation effects on the power MOSFET for space applications. ETRI J 27(4):449–452

    Google Scholar 

  47. Chiang TK (2011) A compact model for threshold voltage of surrounding-gate MOSFETs with localized interface trapped charges. IEEE Trans Electron Devices 58(2):567–571

    Google Scholar 

  48. Chiang TK, Chang DH 2011 A two-dimensional short-channel model for threshold voltage of tri-gate (TG) MOSFETs with localized trapped charges. In IEEE International Conference of Electron Devices and Solid-State Circuits, IEEE, Tianjin, pp 1–3

  49. Gautam R, Saxena M, Gupta RS, Gupta M (2014) Temperature dependent subthreshold model of long channel GAA MOSFET including localized charges to study variations in its temperature sensitivity. Microelectron Reliab 54(1):37–43

    Google Scholar 

  50. Woo JH, Choi JM, Choi YK (2013) Analytical threshold voltage model of junctionless double-gate MOSFETs with localized charges. IEEE Trans Electron Devices 60(9):2951–2955

    Google Scholar 

  51. Long W, Ou H, Kuo JM, Chin KK (1999) Dual-material gate (DMG) field effect transistor. IEEE Trans Electron Devices 46(5):865–870

    Google Scholar 

  52. Liu J, Wen HC, Lu JP, Kwong DL (2005) Dual-work-function metal gates by full silicidation of poly-Si with co-Ni bi-layers. IEEE Electron Device Lett 26(4):228–230

    Google Scholar 

  53. Biswal SM, Baral B, de D, Sarkar A (2015) Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE. Superlattice Microst 82:103–112

    CAS  Google Scholar 

  54. Sarkar A, Das AK et al (2012) Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J 43(11):873–882

    Google Scholar 

  55. Lu Q, et al. (2000) Dual-metal gate technology for deep-submicron CMOS transistors. IEEE Symposium on VLSI Technology. Digest Technic Papers 13:72–73

  56. Zhang Z, Song SC, Huffman C, Hussain MM, Barnett J, Moumen N, Alshareef HN, Majhi P, Sim JH, Bae SH, Lee BH (2005) Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process. Electrochem Solid-State Lett 8(10):G271–G274

    CAS  Google Scholar 

  57. Pal A, Sarkar A (2014) Analytical study of dual material surrounding gate MOSFET to suppress short-channel effects (SCEs). Eng Sci Technol Int J 17(4):205–212

    Google Scholar 

  58. Saurabh S, Kumar MJ (2010) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410

    Google Scholar 

  59. Bari S, De D, Sarkar A (2015) Effect of gate engineering in JLSRG MOSFET to suppress SCEs: an analytical study. Physica E: Low-Dimension Syst Nanostructures 67:143–151

    CAS  Google Scholar 

  60. S Sharma, et al. (2016) Investigation of material engineered junctionless cylindrical gate MOSFET with and without source/drain extension. IEEE International Conference on Inventive Computation Technologies (ICICT) 26: 1–4

  61. Pratap Y, Haldar S, Gupta RS, Gupta M (2015) Localized charge-dependent threshold voltage analysis of gate-material-engineered junctionless nanowire transistor. IEEE Trans Electron Dev 62(8):2598–2605

    CAS  Google Scholar 

  62. Han JW, Moon DI, Sub Oh J, Choi YK, Meyyappan M (2014) Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor. Appl Phys Lett 104(25):253506

    Google Scholar 

  63. Han JW, Ahn JH, Choi YK (2011) Damage immune field effect transistors with vacuum gate dielectric. J Vacuum Sci Technol B Nanotechnol Microelectronics: Mater Process Measurement, Phenomena 29(1):011014

    Google Scholar 

  64. Gautam R, Saxena M, Gupta RS, Gupta M (2013) Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance. IEEE Trans Electron Dev 60(6):1820–1827

    CAS  Google Scholar 

  65. Pratap Y, Haldar S, Gupta RS, Gupta M (2016) Gate-material-engineered Junctionless nanowire transistor (JNT) with vacuum gate dielectric for enhanced hot-carrier reliability. IEEE Trans Device Mater Reliab 16(3):360–369

    CAS  Google Scholar 

  66. Yan H, Choe HS, Nam SW, Hu Y, Das S, Klemic JF, Ellenbogen JC, Lieber CM (2011) Programmable nanowire circuits for nanoprocessors. Nature 470(7333):240–244

    CAS  PubMed  Google Scholar 

  67. Li M, Yeo KH et al (2009) Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate. IEEE Symposium VLSI Technol 16:94–95

    Google Scholar 

  68. Gates BD (2010) Self-assembly: nanowires find their place. Nat Nanotechnol 5(7):484–485

    CAS  PubMed  Google Scholar 

  69. Tekleab D et al. Silicon Nanotube MOSFET. U.S. (2012) Patent Application 13/036,292

  70. Fahad HM, Hussain MM (2012) Are nanotube architectures more advantageous than nanowire architectures for field effect transistors? Sci Rep 2:475

    PubMed  PubMed Central  Google Scholar 

  71. Tiwari PK, Kumar M, Naik RS, Saramekala GK (2016) Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs. J Semicond 37(6):064003

    Google Scholar 

  72. Tekleab D (2014) Device performance of silicon nanotube field effect transistor. IEEE Electron Device Lett 35(5):506–508

    CAS  Google Scholar 

  73. Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11(10):4393–4399

    CAS  PubMed  Google Scholar 

  74. Tiwari PK, Samoju VR, Sunkara T, Dubey S, Jit S (2016) Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs). J Comput Electron 15(2):516–524

    CAS  Google Scholar 

  75. Kumar A, Bhushan S, Tiwari PK (2017) A threshold voltage model of silicon-nanotube-based ultrathin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects. IEEE Trans Nanotechnol 16(5):868–775

    CAS  Google Scholar 

  76. Kumar A, Bhushan S, Tiwari PK (2017) Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects. Superlattice Microst 109:567–578

    CAS  Google Scholar 

  77. Kim K, Fossum JG (2001) Double-gate CMOS: symmetrical-versus asymmetrical-gate devices. IEEE Trans Electron Dev 48(2):294–299

    Google Scholar 

  78. Lim HK, Fossum JG (1983) Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans Electron Devices 30(10):1244–1251

    Google Scholar 

  79. Liu YX et al (2003) Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-fin channel. IEEE Int Electron Dev Meet:18–18

  80. Mathew L et al (2004) CMOS vertical multiple independent gate field effect transistor (MIGFET). IEEE Int SOI Conference 4:187–189

    Google Scholar 

  81. Zhang W, Fossum JG, Mathew L, du Y (2005) Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans Electron Devices 52(10):2198–2206

    Google Scholar 

  82. Shrivastava M, Baghini MS, Sachid AB, Sharma DK, Rao VR (2008) A novel and robust approach for common mode feedback using IDDG FinFET. IEEE Trans Electron Devices 55(11):3274–3282

    Google Scholar 

  83. Nagarajan KK, Srinivasan R (2014) Investigation of tunable characteristics of independently driven double gate FinFETs in analog/RF domain using TCAD simulations. J Comput Theor Nanosci 11(3):821–826

    CAS  Google Scholar 

  84. Ambika R, Srinivasan R (2016) Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation. J Comput Electron 15(3):778–786

    CAS  Google Scholar 

  85. Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans Electron Devices 54(12):3308–3316

    CAS  Google Scholar 

  86. Ghosh D, Parihar MS, Armstrong GA, Kranti A (2012) High-performance junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Lett 33(10):1477–1479

    CAS  Google Scholar 

  87. Sahay S, Kumar MJ (2017) Nanotube junctionless FET: proposal, design, and investigation. IEEE Trans Electron Devices 64(4):1851–1856

    Google Scholar 

  88. Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2016) Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET). Appl PhysA 122(12):1049

    Google Scholar 

  89. Rewari S, Haldar S, Nath V, Deswal SS, Gupta RS (2016) Numerical modeling of subthreshold region of junctionless double surrounding gate MOSFET (JLDSG). Superlattice Microst 90:8–19

    CAS  Google Scholar 

  90. Tayal S, Nandi A (2018) Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications. Mater Sci Semicond Process 80:63–67

    CAS  Google Scholar 

  91. Tayal S, Nandi A (2017) Analog/RF performance analysis of inner gate engineered junctionless Si nanotube. Superlattice Microst 111:862–871

    CAS  Google Scholar 

  92. Kumar R, Kumar A (2020) Hetro-dielectric (HD) oxide-engineered Junctionless double gate all around (DGAA) nanotube field effect transistor (FET). Silicon 15:1–8

    CAS  Google Scholar 

  93. Ambika R, Srinivasan R (2016) Performance analysis of n-type junctionless silicon nanotube field effect transistor. J Nanoelectron Optoelectron 11(3):290–296

    CAS  Google Scholar 

  94. Pratap Y, Haldar S, Gupta RS, Gupta M (2014) Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design. IEEE Trans Device Mater Reliab 14(1):418–425

    Google Scholar 

  95. Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11(10):4393–4399

    CAS  PubMed  Google Scholar 

  96. Scarlet SP, Ambika R, Srinivasan R (2017) Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs. Superlattice Microst 107:178–188

    CAS  Google Scholar 

  97. Singh S, Kumar P, Kondekar PN (2014) Transient analysis & performance estimation of gate inside junctionless transistor (GI-JLT). Int J Electric Comput Electron Commun Eng 8(10):1553–1557

    Google Scholar 

  98. Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, New York

    Google Scholar 

  99. Tayal S, Nandi A (2018) Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance. Cryogenics 92:71–75

    CAS  Google Scholar 

  100. Song Y, Zhang C, Dowdy R, Chabak K, Mohseni PK, Choi W, Li X (2014) III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Lett 35(3):324–326

    CAS  Google Scholar 

  101. Razavi P, Fagas G (2013) Electrical performance of III-V gate-all-around nanowire transistors. Appl Phys Lett 103(6):063506

    Google Scholar 

  102. Razavi P, Fagas G (2013) Electrical performance of III-V gate-all-around nanowire transistors. Appl Phys Lett 103(6):063506

    Google Scholar 

  103. Song Y, Zhang C, Dowdy R, Chabak K, Mohseni PK, Choi W, Li X (2014) III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Lett 35(3):324–326

    CAS  Google Scholar 

  104. Chatterjee N, Gupta A, Pandey S (2017) III–V Junctionless nanowire transistor with high-k dielectric material and Schottky contacts. J Nanoelectron Optoelectron 12(9):925–931

    CAS  Google Scholar 

  105. Reference manual (2017) Genius, 3-D Device Simulator, Version 1.9.2–3. Cogenda Pvt. Ltd, Singapore

    Google Scholar 

  106. Koukab A, Jazaeri F, Sallese JM (2013) On performance scaling and speed of junctionless transistors. Solid State Electron 79:18–21

    Google Scholar 

  107. Lou H et al (2012) A junctionless nanowire transistor with a dual-material gate. IEEE Trans Electron Devices 59(7):1829–1836

    CAS  Google Scholar 

  108. Holtij T et al (2013) Compact model for short-channel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices 61(2):288–299

    Google Scholar 

  109. Gnani E, Gnudi A, Reggiani S, Baccarani G (2012) Physical model of the junctionless UTB SOI-FET. IEEE Trans Electron Devices 59(4):941–948

    Google Scholar 

  110. Gnani E, Gnudi A, Reggiani S, Baccarani G, Shen N, Singh N, Lo GQ, Kwong DL (2012) Numerical investigation on the junctionless nanowire FET. Solid State Electron 71:13–18

    CAS  Google Scholar 

  111. Gnani E, Gnudi A, Reggiani S, Baccarani G (2011) Theory of the junctionless nanowire FET. IEEE Trans Electron Devices 58(9):2903–2910

    Google Scholar 

  112. Wang J, du G, Wei K, Zhao K, Zeng L, Zhang X, Liu X (2014) Mixed-mode analysis of different mode silicon nanowire transistors-based inverter. IEEE Trans Nanotechnol 13(2):362–367

    CAS  Google Scholar 

  113. Baidya A, Lenka TR, Baishya S (2016) Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications. Superlattice Microst 100:14–23

    CAS  Google Scholar 

  114. Darwin S, Samuel TA (2020) A holistic approach on Junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12(2):393–403

    CAS  Google Scholar 

  115. Tayal S, Nandi A (2017) Study of 6T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET. Superlattice Microst 112:143–150

    CAS  Google Scholar 

  116. Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2019) Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed, high frequency digital and analog applications. Microsyst Technol 25(5):1527–1536

    CAS  Google Scholar 

  117. Kumari V, Modi N, Saxena M, Gupta M (2015) Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance. IEEE Trans Electron Devices 62(7):2098–2105

    Google Scholar 

Download references

Acknowledgments

Raj Kumar acknowledges the RGNF (UGC) for the financial assistance and UIET (ECE), Panjab University for providing Lab facility.

Author information

Authors and Affiliations

Authors

Contributions

All the authors have contributed in framing, writing and proofreading the manuscript.

Corresponding author

Correspondence to Shashi Bala.

Ethics declarations

This article does not contain any studies involving animals or human participants performed by any of the authors.

Conflict of Interest

The authors declare that they have no conflicts of interest.

Consent to Participate

Not Applicable.

Consent for Publication

Not Applicable.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Kumar, R., Bala, S. & Kumar, A. Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors. Silicon 14, 1053–1067 (2022). https://doi.org/10.1007/s12633-020-00904-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s12633-020-00904-5

Keywords

Navigation