Abstract
As the IC technology is evolving very rapidly, the feature size of the device has been migrating to sub-nanometre regime for achieving the high packing density. To continue with further scaling of ICs, some novel devices such as multiple-gate silicon-on-insulator (SOI) devices, Gate-All-Around (GAA) nanowire and Nanotube MOSFETs have been proposed by researchers in recent years. The short channel transistor below 10 nm needs to have ultra-sharp junctions at source and drain ends with the channel region. The creation of such a sharp junction is quite challenging process from fabrication point of view. Therefore, junctionless transistors (JLT) were proposed to eradicate junction’s related issues, exhibit full CMOS functionality. The multigate junctionless transistors have been proposed, designed and fabricated. This paper illustrated basic working mechanism and behaviour of the various single and multi-gate junctionless MOSFETs. Junctionless nanowires transistor with single circular gate and gate material engineered techniques has also been explained. From simulation results, it has been observed that junctionless Nanotube GAA MOSFET has shown superior electrical behaviour over the Nanowire GAA MOSFET. Junctionless GaAs-Nanotube MOSFET has shown tremendous response over Junctionless Si-Nanotube MOSFET in terms of leakage and ON current. Junctionless GaAs-Nanotube MOSFET may be observed as alternate candidate for future CMOS applications.
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References
International technology roadmap for semiconductors (ITRS). (2015)
Sze SM (2008) Semiconductor devices: physics and technology. John wiley & sons, Hoboken
Colinge JP (2008) The new generation of SOI MOSFETs. Rom J Inf Sci Technol 11(1):3–15
Young KK (1989) Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans Electron Dev 36(2):399–402
Sharma SK, Jain A, Raj B (2018) Analysis of triple metal surrounding gate (TM-SG) III–V nanowire MOSFET for photosensing application. Opto-Electronics Rev 26(2):141–148
Kim YB (2010) Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans Electr Electron Mater 11(3):93–105
Bala S, Khosla M (2018) Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design. J Comput Electron 17(4):1528–1535
International Technology Roadmap for Semiconductors (ITRS), 2010 update
Colinge JP (2004) Novel gate concepts for MOS devices. In Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No. 04EX850), pp 45–49
Larson JM, Snyder JP (2006) Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans Electron Dev 53(5):1048–1058
Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O'Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5(3):225–229
Kranti A, Yan R, Lee CW et al (2010) Junctionless nanowire transistor (JNT): properties and design guidelines. IEEE Proc European Solid State Device Res Conference 14:357–360
Colinge JP, Lee CW, Ferain I, Akhavan ND, Yan R, Razavi P, Yu R, Nazarov AN, Doria RT (2010) Reduced electric field in junctionless transistors. Appl Phys Lett 96(7):073510
Colinge JP, Lee CW, Akhavan ND, et al. (2011) Junctionless transistors: physics and properties. In: Nazarov A, Colinge JP, Balestra F, Raskin JP, Gamiz F, Lysenko V (eds) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Springer, Berlin, Heidelberg, pp 187–200
Lee CW, Ferain I, Afzalian A, Yan R, Akhavan ND, Razavi P, Colinge JP (2010) Performance estimation of junctionless multigate transistors. Solid State Electron 54(2):97–103
Wang Y, Shan C, Dou Z, Wang LG, Cao F (2015) Improved performance of nanoscale junctionless transistor based on gate engineering approach. Microelectron Reliab 55(2):318–325
Colinge JP, Lee CW, Afzalian A et al (2009) SOI gated resistor: CMOS without junctions. IEEE Int SOI Conference 5:1–2
Colinge JP, Kranti A, Yan R et al (2011) Junctionless nanowire transistor (JNT): properties and design guidelines. Solid State Electron 65:33–37
Skotnicki T, Merckel G, Pedron T (1988) The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects. IEEE Electron Device Lett 9(3):109–112
Jeon DY, Park SJ, Mouis M, Barraud S, Kim GT, Ghibaudo G (2013) Low-temperature electrical characterization of junctionless transistors. Solid State Electron 80:135–141
Skotnicki T (2000) Heading for decananometer CMOS-Is navigation among icebergs still a viable strategy?. In 30th IEEE European Solid-State Device Research Conference, Cork, pp 19–33
Shehata N, Gaber AR, Naguib A et al (2015) 3D multi-gate transistors: concept, operation, and fabrication. J Electr Eng 3:1–4
Colinge JP (2014) Multigate transistors: pushing Moore's law to the limit. In IEEE International Conference on Simulation of Semiconductor Processes and Devices, IEEE, Yokohama, pp 313–316
Razavi P, Fagas G, Ferain I et al (2011) Performance investigation of short-channel junctionless multigate transistors. IEEE Ultimate Integrat Silicon 14:1–3
Gundapaneni S, Ganguly S, Kottantharayil A (2011) Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett 32(3):261–263
Taur Y, Ning TH (2013) Fundamentals of modern VLSI devices. Cambridge University Press, Cambridge
Holtij T, Schwarz M, Kloes A, Iniguez B (2013) Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region. Solid State Electron 90:107–115
Han MH, Chang CY, Jhan YR, Wu JJ, Chen HB, Cheng YC, Wu YC (2013) Characteristic of p-type junctionless gate-all-around nanowire transistor and sensitivity analysis. IEEE Electron Device Lett 34(2):157–159
Holtij T, Schwarz M, Kloes A, Iñíguez B (2012) 2D analytical potential modeling of junctionless DG MOSFETs in subthreshold region including proposal for calculating the threshold voltage. In 2012 13th International Conference on Ultimate Integration on Silicon (ULIS), IEEE, Grenoble
Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Colinge JP (2009) Junctionless multigate field-effect transistor. Appl Phys Lett 94(5):053511
Tai CH, Lin JT, Eng YC, Lin PH (2010) A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer. In 10th IEEE International Conference on Solid-State and Integrated Circuit Technology. IEEE, Shanghai, pp 108–110+
Dehdashti AN, Ferain I, Razavi P et al (2011) Improvement of carrier ballisticity in junctionless nanowire transistors. Appl Phys Lett 98(10):103510
Leung G, Chui CO (2011) Variability of inversion-mode and junctionless FinFETs due to line edge roughness. IEEE Electron Device Lett 32(11):1489–1491
Moon DI, Choi SJ, Duarte JP, Choi YK (2013) Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate. IEEE Trans Electron Devices 60(4):1355–1360
Jin X, Liu X, Lee JH (2013) Modeling of subthreshold characteristics of short channel junctionless cylindrical surrounding-gate nanowire metal–oxide–silicon field effect transistors. Phys Scr 89(1):015804
Tsormpatzoglou A, Dimitriadis CA, Clerc R, Pananakakis G, Ghibaudo G (2008) Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans Electron Devices 55(9):2512–2516
Chiang TK (2012) A new quasi-2-D threshold voltage model for short-channel junctionless cylindrical surrounding gate (JLCSG) MOSFETs. IEEE Trans Electron Devices 59(11):3127–3129
Li C, Zhuang Y, Di S, Han R (2013) Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans Electron Devices 60(11):3655–3662
Xiao Y, Zhang B, Lou H, Zhang L, Lin X (2016) A compact model of subthreshold current with source/drain depletion effect for the short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans Electron Devices 63(5):2176–2181
Pandey RK, Murali KV et al (2010) Crystallographic-orientation-dependent gate-induced drain leakage in nanoscale MOSFETs. IEEE Trans Electron Devices 57(9):2098–20105
Ananthan H, Bansal A, Roy K (2005) Analysis of drain-to-body band-to-band tunneling in double gate MOSFET. In 2005 IEEE International SOI Conference Proceedings, IEEE, Honolulu, pp 159–160
Gundapaneni S, Bajaj M, Pandey RK, Murali KVRM, Ganguly S, Kottantharayil A (2012) Effect of band-to-band tunneling on junctionless transistors. IEEE Trans Electron Devices 59(4):1023–1029
Wu M, Jin X, Kwon HI, Chuai R, Liu X, Lee JH (2013) The optimal design of junctionless transistors with double-gate structure for reducing the effect of band-to-band tunneling. J Semiconduct Technol Sci 13(3):245–251
Poindexter EH (1989) MOS interface states: overview and physicochemical perspective. Semicond Sci Technol 4(12):961–969
Trabzon L, Awadelkarim OO (1998) Damage to n-MOSFETs from electrical stress relationship to processing damage and impact on device reliability. Microelectron Reliab 38(4):651–657
Lho YH, Kim KY (2005) Radiation effects on the power MOSFET for space applications. ETRI J 27(4):449–452
Chiang TK (2011) A compact model for threshold voltage of surrounding-gate MOSFETs with localized interface trapped charges. IEEE Trans Electron Devices 58(2):567–571
Chiang TK, Chang DH 2011 A two-dimensional short-channel model for threshold voltage of tri-gate (TG) MOSFETs with localized trapped charges. In IEEE International Conference of Electron Devices and Solid-State Circuits, IEEE, Tianjin, pp 1–3
Gautam R, Saxena M, Gupta RS, Gupta M (2014) Temperature dependent subthreshold model of long channel GAA MOSFET including localized charges to study variations in its temperature sensitivity. Microelectron Reliab 54(1):37–43
Woo JH, Choi JM, Choi YK (2013) Analytical threshold voltage model of junctionless double-gate MOSFETs with localized charges. IEEE Trans Electron Devices 60(9):2951–2955
Long W, Ou H, Kuo JM, Chin KK (1999) Dual-material gate (DMG) field effect transistor. IEEE Trans Electron Devices 46(5):865–870
Liu J, Wen HC, Lu JP, Kwong DL (2005) Dual-work-function metal gates by full silicidation of poly-Si with co-Ni bi-layers. IEEE Electron Device Lett 26(4):228–230
Biswal SM, Baral B, de D, Sarkar A (2015) Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE. Superlattice Microst 82:103–112
Sarkar A, Das AK et al (2012) Effect of gate engineering in double-gate MOSFETs for analog/RF applications. Microelectron J 43(11):873–882
Lu Q, et al. (2000) Dual-metal gate technology for deep-submicron CMOS transistors. IEEE Symposium on VLSI Technology. Digest Technic Papers 13:72–73
Zhang Z, Song SC, Huffman C, Hussain MM, Barnett J, Moumen N, Alshareef HN, Majhi P, Sim JH, Bae SH, Lee BH (2005) Integration of dual metal gate CMOS on high-k dielectrics utilizing a metal wet etch process. Electrochem Solid-State Lett 8(10):G271–G274
Pal A, Sarkar A (2014) Analytical study of dual material surrounding gate MOSFET to suppress short-channel effects (SCEs). Eng Sci Technol Int J 17(4):205–212
Saurabh S, Kumar MJ (2010) Novel attributes of a dual material gate nanoscale tunnel field-effect transistor. IEEE Trans Electron Devices 58(2):404–410
Bari S, De D, Sarkar A (2015) Effect of gate engineering in JLSRG MOSFET to suppress SCEs: an analytical study. Physica E: Low-Dimension Syst Nanostructures 67:143–151
S Sharma, et al. (2016) Investigation of material engineered junctionless cylindrical gate MOSFET with and without source/drain extension. IEEE International Conference on Inventive Computation Technologies (ICICT) 26: 1–4
Pratap Y, Haldar S, Gupta RS, Gupta M (2015) Localized charge-dependent threshold voltage analysis of gate-material-engineered junctionless nanowire transistor. IEEE Trans Electron Dev 62(8):2598–2605
Han JW, Moon DI, Sub Oh J, Choi YK, Meyyappan M (2014) Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor. Appl Phys Lett 104(25):253506
Han JW, Ahn JH, Choi YK (2011) Damage immune field effect transistors with vacuum gate dielectric. J Vacuum Sci Technol B Nanotechnol Microelectronics: Mater Process Measurement, Phenomena 29(1):011014
Gautam R, Saxena M, Gupta RS, Gupta M (2013) Gate all around MOSFET with vacuum gate dielectric for improved hot carrier reliability and RF performance. IEEE Trans Electron Dev 60(6):1820–1827
Pratap Y, Haldar S, Gupta RS, Gupta M (2016) Gate-material-engineered Junctionless nanowire transistor (JNT) with vacuum gate dielectric for enhanced hot-carrier reliability. IEEE Trans Device Mater Reliab 16(3):360–369
Yan H, Choe HS, Nam SW, Hu Y, Das S, Klemic JF, Ellenbogen JC, Lieber CM (2011) Programmable nanowire circuits for nanoprocessors. Nature 470(7333):240–244
Li M, Yeo KH et al (2009) Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate. IEEE Symposium VLSI Technol 16:94–95
Gates BD (2010) Self-assembly: nanowires find their place. Nat Nanotechnol 5(7):484–485
Tekleab D et al. Silicon Nanotube MOSFET. U.S. (2012) Patent Application 13/036,292
Fahad HM, Hussain MM (2012) Are nanotube architectures more advantageous than nanowire architectures for field effect transistors? Sci Rep 2:475
Tiwari PK, Kumar M, Naik RS, Saramekala GK (2016) Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs. J Semicond 37(6):064003
Tekleab D (2014) Device performance of silicon nanotube field effect transistor. IEEE Electron Device Lett 35(5):506–508
Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11(10):4393–4399
Tiwari PK, Samoju VR, Sunkara T, Dubey S, Jit S (2016) Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs). J Comput Electron 15(2):516–524
Kumar A, Bhushan S, Tiwari PK (2017) A threshold voltage model of silicon-nanotube-based ultrathin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects. IEEE Trans Nanotechnol 16(5):868–775
Kumar A, Bhushan S, Tiwari PK (2017) Analytical modeling of subthreshold characteristics of ultra-thin double gate-all-around (DGAA) MOSFETs incorporating quantum confinement effects. Superlattice Microst 109:567–578
Kim K, Fossum JG (2001) Double-gate CMOS: symmetrical-versus asymmetrical-gate devices. IEEE Trans Electron Dev 48(2):294–299
Lim HK, Fossum JG (1983) Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET's. IEEE Trans Electron Devices 30(10):1244–1251
Liu YX et al (2003) Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross-section Si-fin channel. IEEE Int Electron Dev Meet:18–18
Mathew L et al (2004) CMOS vertical multiple independent gate field effect transistor (MIGFET). IEEE Int SOI Conference 4:187–189
Zhang W, Fossum JG, Mathew L, du Y (2005) Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans Electron Devices 52(10):2198–2206
Shrivastava M, Baghini MS, Sachid AB, Sharma DK, Rao VR (2008) A novel and robust approach for common mode feedback using IDDG FinFET. IEEE Trans Electron Devices 55(11):3274–3282
Nagarajan KK, Srinivasan R (2014) Investigation of tunable characteristics of independently driven double gate FinFETs in analog/RF domain using TCAD simulations. J Comput Theor Nanosci 11(3):821–826
Ambika R, Srinivasan R (2016) Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation. J Comput Electron 15(3):778–786
Kranti A, Armstrong GA (2007) Design and optimization of FinFETs for ultra-low-voltage analog applications. IEEE Trans Electron Devices 54(12):3308–3316
Ghosh D, Parihar MS, Armstrong GA, Kranti A (2012) High-performance junctionless MOSFETs for ultralow-power analog/RF applications. IEEE Electron Device Lett 33(10):1477–1479
Sahay S, Kumar MJ (2017) Nanotube junctionless FET: proposal, design, and investigation. IEEE Trans Electron Devices 64(4):1851–1856
Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2016) Improved analog and AC performance with increased noise immunity using nanotube junctionless field effect transistor (NJLFET). Appl PhysA 122(12):1049
Rewari S, Haldar S, Nath V, Deswal SS, Gupta RS (2016) Numerical modeling of subthreshold region of junctionless double surrounding gate MOSFET (JLDSG). Superlattice Microst 90:8–19
Tayal S, Nandi A (2018) Optimization of gate-stack in junctionless Si-nanotube FET for analog/RF applications. Mater Sci Semicond Process 80:63–67
Tayal S, Nandi A (2017) Analog/RF performance analysis of inner gate engineered junctionless Si nanotube. Superlattice Microst 111:862–871
Kumar R, Kumar A (2020) Hetro-dielectric (HD) oxide-engineered Junctionless double gate all around (DGAA) nanotube field effect transistor (FET). Silicon 15:1–8
Ambika R, Srinivasan R (2016) Performance analysis of n-type junctionless silicon nanotube field effect transistor. J Nanoelectron Optoelectron 11(3):290–296
Pratap Y, Haldar S, Gupta RS, Gupta M (2014) Performance evaluation and reliability issues of junctionless CSG MOSFET for RFIC design. IEEE Trans Device Mater Reliab 14(1):418–425
Fahad HM, Smith CE, Rojas JP, Hussain MM (2011) Silicon nanotube field effect transistor with core–shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett 11(10):4393–4399
Scarlet SP, Ambika R, Srinivasan R (2017) Effect of eccentricity on junction and junctionless based silicon nanowire and silicon nanotube FETs. Superlattice Microst 107:178–188
Singh S, Kumar P, Kondekar PN (2014) Transient analysis & performance estimation of gate inside junctionless transistor (GI-JLT). Int J Electric Comput Electron Commun Eng 8(10):1553–1557
Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, New York
Tayal S, Nandi A (2018) Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance. Cryogenics 92:71–75
Song Y, Zhang C, Dowdy R, Chabak K, Mohseni PK, Choi W, Li X (2014) III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Lett 35(3):324–326
Razavi P, Fagas G (2013) Electrical performance of III-V gate-all-around nanowire transistors. Appl Phys Lett 103(6):063506
Razavi P, Fagas G (2013) Electrical performance of III-V gate-all-around nanowire transistors. Appl Phys Lett 103(6):063506
Song Y, Zhang C, Dowdy R, Chabak K, Mohseni PK, Choi W, Li X (2014) III-V junctionless gate-all-around nanowire MOSFETs for high linearity low power applications. IEEE Electron Device Lett 35(3):324–326
Chatterjee N, Gupta A, Pandey S (2017) III–V Junctionless nanowire transistor with high-k dielectric material and Schottky contacts. J Nanoelectron Optoelectron 12(9):925–931
Reference manual (2017) Genius, 3-D Device Simulator, Version 1.9.2–3. Cogenda Pvt. Ltd, Singapore
Koukab A, Jazaeri F, Sallese JM (2013) On performance scaling and speed of junctionless transistors. Solid State Electron 79:18–21
Lou H et al (2012) A junctionless nanowire transistor with a dual-material gate. IEEE Trans Electron Devices 59(7):1829–1836
Holtij T et al (2013) Compact model for short-channel junctionless accumulation mode double gate MOSFETs. IEEE Trans Electron Devices 61(2):288–299
Gnani E, Gnudi A, Reggiani S, Baccarani G (2012) Physical model of the junctionless UTB SOI-FET. IEEE Trans Electron Devices 59(4):941–948
Gnani E, Gnudi A, Reggiani S, Baccarani G, Shen N, Singh N, Lo GQ, Kwong DL (2012) Numerical investigation on the junctionless nanowire FET. Solid State Electron 71:13–18
Gnani E, Gnudi A, Reggiani S, Baccarani G (2011) Theory of the junctionless nanowire FET. IEEE Trans Electron Devices 58(9):2903–2910
Wang J, du G, Wei K, Zhao K, Zeng L, Zhang X, Liu X (2014) Mixed-mode analysis of different mode silicon nanowire transistors-based inverter. IEEE Trans Nanotechnol 13(2):362–367
Baidya A, Lenka TR, Baishya S (2016) Mixed-mode simulation and analysis of 3D double gate junctionless nanowire transistor for CMOS circuit applications. Superlattice Microst 100:14–23
Darwin S, Samuel TA (2020) A holistic approach on Junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12(2):393–403
Tayal S, Nandi A (2017) Study of 6T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET. Superlattice Microst 112:143–150
Rewari S, Nath V, Haldar S, Deswal SS, Gupta RS (2019) Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed, high frequency digital and analog applications. Microsyst Technol 25(5):1527–1536
Kumari V, Modi N, Saxena M, Gupta M (2015) Theoretical investigation of dual material junctionless double gate transistor for analog and digital performance. IEEE Trans Electron Devices 62(7):2098–2105
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Raj Kumar acknowledges the RGNF (UGC) for the financial assistance and UIET (ECE), Panjab University for providing Lab facility.
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Kumar, R., Bala, S. & Kumar, A. Study and Analysis of Advanced 3D Multi-Gate Junctionless Transistors. Silicon 14, 1053–1067 (2022). https://doi.org/10.1007/s12633-020-00904-5
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DOI: https://doi.org/10.1007/s12633-020-00904-5