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Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell

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Abstract

Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.

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Authors and Affiliations

  1. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran

    Sepehr Tabrizchi

  2. Department of Electrical and Computer Engineering, Graduate University of Advanced Technology, Kerman, Iran

    Fazel Sharifi & Parisa Dehghani

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  1. Sepehr Tabrizchi
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  2. Fazel Sharifi
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  3. Parisa Dehghani
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Correspondence to Fazel Sharifi.

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Tabrizchi, S., Sharifi, F. & Dehghani, P. Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. Circuits Syst Signal Process 40, 3523–3535 (2021). https://doi.org/10.1007/s00034-020-01638-w

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