Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors
Introduction
As the physical size of field-effect transistors (FETs) continues to scale down, the number of integrated devices in a single die increases multiplicatively, accompanied by an increase in chip performance. However, the scaling trend of the threshold voltage (VTH) does not follow the scaling trend of the physical size of chips, limiting the reduction of supply voltage (VDD) and resulting in higher power consumption density. In some power-hungry applications with a large number of transistors [[1], [2], [3]], power consumption is a problem that cannot be ignored. This problem is directly related to the limit of 60 mV/decade sub-threshold swing (SS) at room temperature, also known as Boltzmann tyranny. Negative capacitance FETs (NCFETs), owing to their ability to achieve an SS of sub-60 mV/decade, are considered to be a promising technology for the next generation of integrated circuits. This is because NCFETs, with their integrated ferroelectric layer in the gate stack, enable internal gate-voltage amplification, thus lowering VTH and increasing the switching current ratio (ION/IOFF) [4]. Recently, many studies have explored device design using various NCFET structures, such as 3-D FinFET [[5], [6], [7]], 2-D fully depleted silicon-on-insulator transistors (FDSOI) [8,9], and double-gate junctionless transistors [10]. HfO2-based ferroelectric materials have been proven to exhibit superior performance because of their better compatibility with CMOS processes. A series of experiments yielding consistent results have also been reported [[11], [12], [13], [14], [15]]. Furthermore, Process variations such as random discrete doping (RDD) [16], line-edge roughness (LER) [17] and work function variation (WFV) [18], have been investigated for NCFET. These variation sources have been recognized as primary causes for device variability in advanced transistors and negative capacitance transistors have been proved to suppress them. Temperature variation is also an important factor affecting device performance. Many studies have shown that the negative capacitance effect of NCFET decreases with the increase of temperature, and when the temperature is lower, hysteresis will occur [[19], [20], [21]].
The internal voltage amplification mechanism of NCFETs is their main advantage, and this amplification can be adjusted by tuning the material parameters of the ferroelectric layer [22,23]. In addition, the reduced and even negative drain-induced barrier lowering (DIBL) effect as well as the negative differential resistance (NDR) effect in NCFETs have also been investigated [[24], [25], [26], [27], [28], [29]]. The NDR effect, which originates from the coupling of the drain voltage to the internal gate voltage via gate-to-drain capacitance, causes a current loss [24]. It has been reported that under a certain gate voltage (VG), properly increasing the thickness of the ferroelectric layer (TFE) makes the NDR effect more obvious, and when TFE is unchanged, the NDR effect is more easily observed at low VG [26]. However, there is still a lack of detailed research on the inherent relationship between the DIBL and NDR effects caused by the negative capacitance effect, which is particularly important for the design of ultra-small FETs. In this work, we mainly analyze the influence of drain bias on the internal gate voltage under different ratios of ferroelectric parameters to elucidate the inherent correlation between these two effects.
Section snippets
Device structure of negative capacitance FETs
The key process steps and FDSOI structure (generated using TCAD Sentaurus) are shown in Fig. 1(a) and (b), respectively. The ferroelectric capacitor is connected in series on the gate contact, and the device parameters of the underlying FDSOI FET are shown in Table 1, where the threshold voltage (VT) is calculated for ID = 0.1μA/μm. The simulated process flow and device dimensions are similar to those of the UTB (ultra-thin body)-FDSOI MOSFETs presented in Ref. [30]. The process flow includes
Negative DIBL effect in NCFETs
Fig. 2 shows the ID–VG characteristics of the FDSOI and the NCFET at VD = 0.05 V and VD = 0.7 V. The DIBL effect in the FDSOI is 73.8 mV/V, as shown in Fig. 2(a). The NCFET has a good inhibitory effect on DIBL compared with its FDSOI counterpart. As the ferroelectric thickness (TFE) increases, the DIBL effect is significantly reduced and even negative valuesappear, as shown in Fig. 2 (b), (c), and (d). In addition to TFE, Pr and Ec are other important parameters in NCFET performance
Conclusion
In NCFETs, an increase in VD causes VIN to decrease, which not only suppresses the DIBL effect but also causes the NDR phenomenon in the output characteristics. We have shown that DIBL tends to be consistent in NCFETs with the same RPE, despite them exhibiting different current intensities in the strong inversion region. With regard to different RPE, the DIBL effect decreases as RPE decreases because CFE decreases. Therefore, within a valid range of ferroelectric parameters, RPE can be directly
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
This work is supported by the National Natural Science Foundation of China (grant 62071160), and Zhejiang Provincial Natural Science Foundation of China (grant LY18F040005).
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