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Efficient HW/SW partitioning of Halo: FPGA-accelerated recursive proof composition in blockchain

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Abstract

The blockchain space has seen tremendous innovation and advancement, in the last few years with an explosion of functionality and use cases. However, several challenges naturally arise from the nature of these distributed systems—energy efficiency, privacy, and scalability challenges due to the computational resources required to generate, validate, and store the cryptographic proofs that provide immutable security. New applications of recursive proof composition offer paradigmatic improvements that effectively address these challenges. This paper addresses the practical implementation of these theoretical advances. We demonstrate how HW/SW co-design methods can be algorithmically applied to identify practical hardware optimizations for the cryptographic verification of these zero-knowledge proofs, using Halo as an example. We offer a partitioning methodology of blockchain operations and then discuss the use of the Binary Particle Swarm Optimization (BPSO) algorithm for systemic optimization. To demonstrate our methodology, we implement the Halo algorithm on the Xilinx Zynq-7000 System-on-Chip (SoC). We successfully achieve a considerable speedup of 2.2x, compared to a software-only implementation on a CPU.

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Acknowledgements

This work was conducted in collaboration with the Decentralized Consensus (Blockchain Engineering) Group at Insight.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Santa Clara University, Santa Clara, CA, 95053, USA

    Rami Akeela & Mitchell P. Krawiec-Thayer

  2. Head of Research, Insight, San Francisco, CA, 94107, USA

    Rami Akeela & Mitchell P. Krawiec-Thayer

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  1. Rami Akeela
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Correspondence to Rami Akeela.

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Akeela, R., Krawiec-Thayer, M.P. Efficient HW/SW partitioning of Halo: FPGA-accelerated recursive proof composition in blockchain. Microsyst Technol 27, 3559–3569 (2021). https://doi.org/10.1007/s00542-020-05138-4

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