Abstract
In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.
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1 Introduction
Continuous scaling of MOSFET increases the performance of integrated circuits (ICs) in terms of speed and device density. The scaling of MOSFET poses some challenges due to increase in leakage in sub-threshold region. The scaling of threshold voltage increases the leakage current which limits the functionality of circuits [1]. The dominant component of leakage current is the off-state or sub-threshold current in the devices. The leakage reduction methods are devised at processing level as well as circuit level to overcome the leakage current.
The methods which reduce leakage power at circuit level include transistor stacking, multiple threshold voltage (Vth), multiple power supply (Vdd), dynamic Vdd and dynamic Vth [2]. The continuous miniaturization of transistor’s dimensions result in advancement in performance, but the continual scaling is not following the same trend as it used to follow from the past few decades i.e. there arises complications because of the process technology limits and fundamental materials.
Leakage power reduction is the demanding factor for all the portable systems so that battery life can be improved [3]. In this paper, we are focusing the benefits of FinFET over MOS device because FinFET comes up with efficient PDP in comparison to the MOS device. Short channel planner devices suffer the limitations such as shift in threshold voltage, drain induced barrier lowering (DIBL) and change in sub-threshold slope. These all factors result large off-state current. It is necessary to increase the gate control by using double or triple gate devices for reducing the off-state current. Therefore, FinFET can be a good choice as it improves electrostatic characteristics of a device which improves the characteristics of short channel devices.
FinFET devices have a thin silicon body to which gate electrodes are wrapped. These devices are called quasi-planner because current flows parallel to wafer plane. In FinFET, etching of gate electrode at the top of channel makes the gates to have independent control. Gate width of FinFET is ‘2nh’ where n is the number of fins and h denotes fin height. The number of fins can be increased which forms the wider FinFET to have high on-state current [4, 5]. FinFET device consists of two general configurations such as shorted-gate (SG) and independent gate (IG). The basic structure of FinFET device is shown in Fig. 1.
Basic structure of FinFET device
Two gates are connected together in SG FinFET while in case of IG FinFET configuration, the top portion of the gate is etched away that results in the formation of two IGs which can be controlled separately, hence offers more options of design. It seems that as the controllability increases, the leakage power can be optimize in a better way in comparison to the existing MOS devices [6, 7].
Several leakage reduction techniques are devised from the past few decades. The expression for the leakage power is given as shown in Eq. 1.
where Vdd is supply voltage and Ileakage is the aggregate leakage current due to all components of leakage. The main cause of leakage is the reduction of threshold voltage which contributes huge amount of leakage current. So, it is important to reduce the leakage current in nanoscale regime. Various techniques are used to reduce leakage current both at process and circuit levels. Leakage current can be controlled by controlling channel length, oxide thickness, junction depth and doping profile at process level. However, at circuit level, leakage can be controlled by controlling drain, gate, source and body (substrate) voltages, besides by threshold voltage as well.
Various techniques are developed from time to time to reduce leakage power dissipation at circuit level. These techniques include use of transistors stacking, multiple threshold technology and body biasing. Off-state transistors in stacking fashion in the circuit reduces the leakage power dissipation. The leakage current decreases as the number of off-state stacking transistors are increased. Threshold voltages of stacking transistors can be controlled by controlling gate to source voltage, drain to source voltage and substrate to source voltage [8, 9]. Stacking of transistors has its own disadvantages that it leads to performance degradation and large propagation delay [10, 11].
Multiple-Vth approach has both high Vth as well as low Vth transistors and used on the single wafer. Low Vth circuits are used to improve performance while high Vth circuits are used to reduce the leakage current. Multiple-Vth can be achieved by the methods like Multiple channel doping, Multiple oxide layers, Multiple channel length and multiple body bias [2]. Moreover, design technique like multiple-threshold CMOS was also one of the method used to reduce the propagation delay [12]. LECTOR and INDEP leakage reduction approaches are the CMOS based special configurations of the transistors and explained as below:
1.1 LECTOR technique
Continuous device scaling increases the sub-threshold leakage current and to reduce the sub-threshold leakage current, we can use LECTOR technique. LECTOR technique contains two extra transistors between pull-up and pull-down networks in such a way that gate terminal of one leakage control transistor (LCT) is controlled by the source terminal of other. It increases the resistance of the path from Vdd to ground. One of the LCT is always near cut-off region and decreases the leakage current. There is no need of any control circuit to examine the states of extra included transistors [13]. The schematic arrangement of LECTOR technique is shown in Fig. 2.
Schematic arrangement of LECTOR technique
1.2 INDEP technique
This is the approach to reduce the leakage in logic circuits by controlling the inputs of the extra inserted transistors which are inserted between pull-up and pull-down networks. This technique is called INDEP technique because gate terminals of extra inserted transistors are controlled by input combinations. Suitable selection of inputs at gate terminals of the INDEP transistors decreases large leakage current. It overcomes the problem of large propagation delay. The threshold voltage of INDEP transistors is chosen in such a way that it matches with the pull-down and pull-up networks [11]. The logical view of the INDEP approach is depicted in Fig. 3.
Schematic view of INDEP approach
Rest of the paper is organized as follows. Section 2 presents the comparative analysis of CMOS and FinFET logic gates in terms of leakage power dissipation, propagation delay and PDPs for all input combinations. FinFET LECTOR approach and FinFET INDEP approach is extensively discussed in Sect. 3. Section 4 discussed the obtained simulation results of FinFET logic gates. Finally, the paper is concluded in Sect. 5.
2 Comparison of various performance metrics of MOSFET and FinFET
The comparison of various performance metrics like leakage power dissipation, propagation delay and PDP are carried out in case of CMOS inverter, CMOS 2-input NAND (NAND2), CMOS 2-input NOR (NOR2), FinFET inverter, FinFET NAND2 and FinFET NOR2 gates. The comparative analysis is taken to identify the benefits of FinFETs over MOS devices. The circuits are simulated at 16 nm technology node using multi-gate Berkeley Short-channel IGFET Model4 (MG BSIM4) predictive technology model (PTM) [14] and the comparative results are tabulated in Table 1. The results are verified by the circuit simulations [15, 16] using Mentor Graphics ELDO simulator at room temperature with power supply of 0.9 V. The channel lengths of N and P-FinFET devices are equal and 16 nm while the channel widths for N and P-FinFET devices are 32 nm and 64 nm respectively. The height of FinFET (hfin) devices are 28 nm, the width of FinFET (tfin) devices are 12 nm and number of fins (nfin) are 1. Leakage power dissipations are calculated for all the input combinations and overall leakage power dissipation is the summation of all the input combinations. Propagation delay is the worst delay value among the combinations. PDP is the product of leakage power dissipation and delay values.
The simulation results show that leakage power dissipation in FinFET inverter, FinFET NAND2 and FinFET NOR2 gates are decreased by 96.48%, 99.75% and 99.76% respectively in comparison to the CMOS inverter, CMOS NAND2 and CMOS NOR2 gates. This is because of decreasing in short channel effects in FinFET logic circuits. These results clearly infer that leakage is lower in case of FinFET circuits as compared to CMOS logic circuits. The speed of FinFET circuits are fast as compared to CMOS circuits because two gates are used. PDP is improving for FinFET circuit and it is the figure of merit for the logic circuits. Therefore, FinFET proved a best substitute for MOSFET. The transient behavior of FinFET NAND2 and FinFET NOR2 gates are shown in Figs. 4 and 5.
Transient behavior of FinFET NAND2 gate
Transient behavior of FinFET NOR2 gate
3 FinFET logic gates design
3.1 FinFET LECTOR gates
LECTOR technique was devised for CMOS logic to overcome the leakage current [13]. In this paper, LECTOR technique is used to design FinFET logic gates. There are two leakage control FinFETs between pull-up and pull-down networks of logic gates in LECTOR with FinFET logic. N and P-FinFETs are introduced in such a manner that gates of each leakage control FinFET is controlled by the source terminal of the other. One of the leakage control FinFET is always near its cut-off voltage for any combination of inputs that reduces leakage current. The reduction in leakage current is due to the stacking of transistors in the path from power supply to ground. FinFET logic gates with LECTOR technique like FinFET inverter, FinFET NAND2 and FinFET NOR2 gates are designed and simulated. The logic configurations for FinFET inverter, FinFET NAND2 and FinFET NOR2 gates are shown in Figs. 6, 7 and 8 respectively.
SG FinFET LECTOR inverter
SG FinFET LECTOR NAND2 gate
SG FinFET LECTOR NOR2 gate
The gate terminals of the leakage control FinFETs are connected to the source terminal of the other leakage control FinFET. The switching is controlled by voltage potential at the sources of the leakage controlled N and P-FinFETs. For any input combination, it is ensured that one of the LECTOR FinFET is near its cut-off region. The simulation results for FinFET LECTOR inverter, FinFET LECTOR NAND2 and FinFET LECTOR NOR2 gates are presented in Table 2 for leakage power dissipation, propagation delay and PDP.
The simulation results show that there is reduction in leakage power dissipation and PDP as compared to conventional one. The simulation data for conventional circuits are presented in Table 1. Leakage power dissipation is decreased by 20.85%, 15.42% and 36.83% respectively for FinFET LECTOR inverter, FinFET LECTOR NAND2 and FinFET LECTOR NOR2 gates as compared to conventional FinFET logic gates. This is due to the transistors stacking effect that leakage power dissipation is reduced.
3.2 FinFET INDEP gates
Low leakage INDEP technique is applied to FinFET logic gates and observed the huge amount of reduction in leakage current. Two extra FinFETs are inserted between pull-up and pull-down networks and the gate terminals are depending on primary input combinations of logic circuits. INDEP technique reduces the leakage power dissipation and provides rail to rail output voltage swing if the inputs to the gate terminals are appropriate based on Boolean logic. Besides, it overcomes the problem of high propagation delay which exists with stacking of transistors. INDEP technique can be applied in both active and standby modes. The extra inserted FinFETs between pull-up and pull-down networks form stacks for different input combinations. The SG FinFET inverter, FinFET NAND2, FinFET NOR2 gates with INDEP approach are shown in Figs. 9, 10 and 11 respectively.
SG FinFET INDEP inverter
SG FinFET INDEP NAND2 gate
SG FinFET INDEP NOR2 gate
FinFET inverter circuit consists of two inputs V1 and V2 for the extra inserted transistors as shown in Fig. 9. These inputs are directly connected to the primary input for getting the appropriate output with reduced leakage power. FinFET NAND2 gate with two INDEP FinFETs are shown in Fig. 10. When we have same inputs i.e. \(In1 = In2 = 0 0= 11\) then \(V1 = V2 = In1 = In2\) and in case of input states like “01” and “10” conditions then the values of V1 and V2 are set so as to fulfill the logic and gives the output accordingly. The simulation results for FinFET INDEP circuits are listed in Table 3. FinFET INDEP NAND2 gate is capable of saving large amount of leakage power as observed from Table 3. This approach proves the improvement in PDP in comparison to the conventional CMOS NAND2 gate. The leakage power for input combinations “10” and “01” are less leaky in comparison to the state with “11” and more leaky than the “00” state.
In case of FinFET INDEP NOR2 gate, two INDEP FinFETs are placed between pull-up and pull-down networks as shown in Fig. 11. \(V1 = V2 = In1 = In2\) for the same input combinations i.e. “00” and “11” states. The inputs V1 and V2 are chosen in such a way so that it satisfies the logic for “01” and “10” states. \(V1 = V2 = 1\) for the primary input combinations “01” and “10” that fulfills the logic for INDEP FinFET NOR2 gate. It can be observed from Table 3 that FinFET NAND2 implementation of INDEP logic is superior in comparison to FinFET INDEP NOR2 implementation and state “00” is the best state for leakage reduction for both FinFET NAND2 and FinFET NOR2 gates.
Leakage power dissipation is reduced by 68.33%, 58.87% and 65.70% in FinFET INDEP inverter, FinFET INDEP NAND2 and FinFET INDEP NOR2 gates respectively in comparison to the conventional FinFET logic gates. PDP is improved for INDEP approach due to huge reduction of leakage power with minimum propagation delay. FinFET with INDEP shows better result as compared to FinFET with LECTOR.
A comparison is made among conventional FinFET, FinFET with LECTOR and FinFET with INDEP approaches for checking the output responses by considering the transient behavior. The transient responses for different circuits are depicted in Fig. 12. FinFET with INDEP approach provides exact output similar to conventional one while level distortion is seen in LECTOR with FinFET technique as shown in Fig. 12. The charging and discharging of load capacitor in INDEP technique is proper due to the logic arrangement.
Transient analysis of different techniques
4 Simulation results and discussion
The simulation results for conventional FinFET, FinFET with LECTOR and FinFET with INDEP techniques are presented in this section. All the experimental data and results are obtained at 16 nm MG BSIM4 PTM technology node using ELDO simulator at room temperature with Vdd = 0.9 V. Circuits are tested for leakage power dissipation, propagation delay and PDP. The total leakage power dissipation is the summation of leakage power components for all input combinations and the propagation delay is the highest delay obtained from the difference between the 50% transition of the input and output signals and finally we obtained PDP by multiplying the respective leakage power dissipation and propagation delay. This gives us average energy consumption per switching event in logic circuits and this quantity gives us the idea about performance of digital logic circuits. DC characteristics is used to measure the critical voltage levels and useful to identify the accurate operation of the logic techniques. DC characteristic of different methods for FinFET inverter are shown in Fig. 13.
Comparative DC analysis of different methods
The comparison is made among the conventional FinFET, FinFET with LECTOR and FinFET with INDEP techniques and the results show that FinFET with INDEP is giving the better DC characteristics in comparison to others as depicted from Fig. 13. The intermediate nodes are responsible for improver response at output in FinFET with LECTOR technique while in INDEP FinFET logic circuit, there is no loss of rail to rail swing voltage at output node. The results are clearly depicted that FinFET with INDEP approach is efficient one as the results are closer to ideal behavior as can be clearly observed from Fig. 13.
PVT variations are significantly affecting the logic circuits at nanoscaled regime. The behavior of the PVT variations are checked for FinFET with INDEP technique. PVT variations for FinFET INDEP ring oscillator is observed by considering the related parameters. Figure 14 is showing the leakage power dissipation for INDEP ring oscillator with Vdd variations for both input logics.
Power dissipation versus supply voltage variations
Power dissipation is increasing when Vdd increases due to its direct dependency on supply voltage. When we are increasing the supply voltage from 0.5 to 0.8 V, the power dissipation shows the measurable increase for both logics. The power dissipation is also depending on the width of the transistors that is the process parameter. The power dissipation with the variations in width of transistors for both input logics is shown in Fig. 15.
Power dissipation versus width of transistors variations
Figure 15 clearly shows that power dissipation at logic ‘1’ is large as compared to logic ‘0’. When the width of transistors is doubled then power dissipation is increasing for both logic levels. The environmental effect in term of temperature is explored for leakage power dissipation. The power dissipation with temperature variation is depicted in Fig. 16.
Power dissipation versus temperature (°C) variations
Carrier concentration increases by huge amount with the increase in temperature, this increases the power dissipation to huge extent as can be observed from Fig. 16.
Leakage power dissipation, propagation delay and PDP are calculated for ring oscillator at 16 nm technology node for FinFET, FinFET with LECTOR and FinFET with INDEP approaches. Table 4 represents the performance metrics for the ring oscillator circuit which also depicts that FinFET with INDEP approach is the best leakage reduction technique because it is not only reducing the leakage power dissipation but also improving the energy efficiency of the logic circuits by reducing the PDP metric.
The reliability of the logic circuits is measured by calculating the uncertainties of the logic circuits. The uncertainties are the ratio of standard deviation to mean value of the distribution. Lower value of uncertainty is desired for less PVT variations. The standard deviation and mean are the significant observed values for the distribution to find out the reliability of the circuits. The statistical parameters are obtained by running the Monte-Carlo simulation for 1000 samples. Simulation is run for ± 10% variations in PVT parameters under 3σ Gaussian random distribution. Figure 17 shows the Monte-Carlo distribution for ring oscillator circuit. The uncertainty for INDEP circuit is lowest as compared to conventional and LECTOR circuit. It shows the reliability of INDEP circuit is more as compared to others.
Monte-Carlo distribution for PDP
5 Conclusion
The leakage power dissipation is the major issue in modern semiconductor industry. FinFET devices have the advantages such as lower power dissipation and future scalability over MOS devices. It added the fuel to next generation of ICs. A comparative and comprehensive analysis is carried out in this paper for comparison between the MOS and FinFET devices. It is identified that FinFET is the best suitable replacement of MOS devices due to its lower power dissipation. INDEP and LECTOR leakage reduction approaches are utilized for designing the logic circuits using FinFET devices and compared with the conventional designs using Mentor Graphics ELDO simulator at 16 nm technology node. It has been observed that INDEP approach provides large saving of the leakage power as compared to LECTOR and conventional designs. The leakage power dissipation is saved by 94.91% in case of INDEP approach while it is 74.65% in case of LECTOR approach as compared to conventional design for ring oscillator. The PDP is improved by 97.58% in INDEP approach while it is 84.66% in LECTOR technique as compared to conventional design. The reliability analysis for ring oscillator using INDEP approach is checked and verified using Monte-Carlo simulations.
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Mushtaq, U., Sharma, V.K. Performance analysis for reliable nanoscaled FinFET logic circuits. Analog Integr Circ Sig Process 107, 671–682 (2021). https://doi.org/10.1007/s10470-020-01765-z
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DOI: https://doi.org/10.1007/s10470-020-01765-z