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On the logic performance of bulk junctionless FinFETs

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Abstract

In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring oscillator is estimated from its frequency of oscillation, and (iii) the static noise margin of a 6 T SRAM cell is evaluated from its butterfly plot. A three-dimensional numerical device and mixed-mode circuit simulator is used for the performance estimation. CMOS circuits implemented with bulk JL devices are found to have comparable logic performance with their SOI JL counterparts.

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Acknowledgements

Mrs. Monali Sil thanks the Human Research Development group (HRDG), Government of India, for funding the senior research fellowship under reference 09/028(1027)/2018-EMR-I through Council of Scientific and Industrial Research (CSIR). The authors also thank the University of Calcutta for providing the necessary infrastructural support.

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  1. Department of Electronic Science, University of Calcutta, Kolkata, 700009, India

    Monali Sil & Abhijit Mallik

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  1. Monali Sil
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Correspondence to Monali Sil.

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Sil, M., Mallik, A. On the logic performance of bulk junctionless FinFETs. Analog Integr Circ Sig Process 106, 467–472 (2021). https://doi.org/10.1007/s10470-020-01782-y

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