Real-time automated register abstraction active power-aware electronic system level verification framework

Highlights

• The proposed verification architecture supports active power management, TLM stimulus-based functional verification, automated register abstraction layer verification and automated coverage and power checks. The testbench architecture attains the following objectives of power-aware management and functional verification Intent:

  • Simulations of power-aware management unified power format (UPF) architecture using electronic system level (ESL) abstraction for early verification. Visualization of failure, isolation or retention. Automatic power checks for power management errors.

  • Addition of transaction-level modeling based stimulus generation in testbench for functional verification of design with assertion based self-checking mechanism.

  • Automated register abstraction layer implementation on testbench for register power-aware verification.

  • Collection of power states, transition coverage and functional coverage with automated coverage and power checks.

  • Implementation of real-time automation for valid scenario generation in minimum execution time.

Abstract

All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM).

Introduction

The world is demanding “always on” integrated contents like audio, video, data and memory modules on the SoC in digital format. The more integrated content needs more concurrency in design, which makes it harder to verify a system. The traditional tools and techniques are no longer sufficient for verification of these massively integrated contents [1]. There is also a persistent push to make the system energy efficient, it also results in increasing complexity. It is of utmost importance to catch the power consumption issues early in the implementation phase of the design cycle. The UPF 2.1 adhesion enables early power consideration in the design implementation phase [2]. The UPF defines the design power intent. UPF 2.1 library permits the Power-Aware Verification (PAV) at the ESL stage of design development with synthesized netlist generation using automated simulation-based verification [3]. A faster verification architecture is required with the early checks to encounter bugs before physical implementation. The ESL design and verification is currently an important field of research.

This paper presents Universal Verification Methodology (UVM) testbench architecture which supports stimulus-based functional verification and power-aware verification at multiple levels of abstraction. The proposed testbench flow accelerates the design verification and improves the coverage closure. It also directs the automated power checks and power-state coverage data collection with the power management reporting mechanism. Dynamic power is due to the continual toggling of power-consuming clocks between ‘on’ and ‘off’ states. When the SoC is off, it should not draw any current, but there is a continuous current due to source-drain reverse bias diffusion and inversion current under threshold voltage at the gate. The power consumed by this leakage current is called static leakage power. Static power is categorized as leakage and standby. Standby power consumption is a continuous consumption from VDD to ground. As the size of the device reduces, static leakage power becomes more critical. Static leakage power is the chief concern in the verification of active power management. The power management is done in the later phases of the design cycle because power specification libraries do not support high-level languages like SystemVerilog and UVM. There are very few approaches working on early-stage power-aware verification. SystemC power gating technique uses specific class data types and clock synchronization as defined in conventional work [4]. The other early power-aware verification advancement is through pin-signal driven power architectures using UPF 1.0 with precise cycle-accurate SystemC design models [5]. SystemC modeling offers a crucial trade-off between speed and accuracy.

It is essential to consider power throughout the design process with concurrent verification and equivalence checking [6]. It is best to design and verify power management upfront because of the maximum available flexibility to exert the impactful leverage on the result. The system abstraction level and architectural design flow are shown in Fig. 1. The higher the abstraction level, the higher the flexibility. The ESL level golden macro-architecture gives an edge over RTL level micro-architecture to catch design issues earlier. Graphic Design System II (GDSII) layout is the final product of the SoC design cycle for IC fabrication at physical level of abstraction.

The proposed verification architecture supports active power management, TLM stimulus-based functional verification, automated register abstraction verification and automated coverage and power checks, as shown in Fig. 2. The testbench architecture attains the following objectives of power-aware management and functional verification intent:

• Simulations of power-aware management UPF architecture using ESL abstraction for early verification. Visualization of failure, isolation or retention. Automatic power checks for power management errors.

• Addition of transaction-level modeling based stimulus generation in testbench for functional verification of design with assertion based self-checking mechanism [7].

• Automated register abstraction layer implementation on testbench for register power-aware verification.

• Collection of power states, transition coverage and functional coverage with automated coverage [8] and power checks.

The existing methods related to the register database abstraction and ESL power-aware verification are discussed in Sec. 2. The proposed testbench architecture of register abstract behavior database creation with ESL power-aware management verification flow is analyzed in Sec. 3.1 Automated register access, 3.2 Active power-aware simulation verification flow. This paper proposes two different paths for verification: frontdoor and backdoor. Frontdoor path provides greater flexibility and functional coverage but is relatively slower as compared to backdoor path. We have proposed algorithm 1 to select the minimum test path among the similar test paths using MINIMIN search and α-trimming function is explained in Sec 3.3. Sec. 4 explains the case study of three and five power domains to test the results. This experimentation identifies that for small designs, the proposed architecture is not as precise as it is for big SoCs. The ESL simulation, ESL power model generation and power error estimation on 20 power domain SoC ©NXP Semiconductors is discussed in Sec. 5. The experiment results supporting the benefits of the contribution are discussed in Sec. 6. Sec. 7 concludes this paper.