Real-time automated register abstraction active power-aware electronic system level verification framework
Introduction
The world is demanding “always on” integrated contents like audio, video, data and memory modules on the SoC in digital format. The more integrated content needs more concurrency in design, which makes it harder to verify a system. The traditional tools and techniques are no longer sufficient for verification of these massively integrated contents [1]. There is also a persistent push to make the system energy efficient, it also results in increasing complexity. It is of utmost importance to catch the power consumption issues early in the implementation phase of the design cycle. The UPF 2.1 adhesion enables early power consideration in the design implementation phase [2]. The UPF defines the design power intent. UPF 2.1 library permits the Power-Aware Verification (PAV) at the ESL stage of design development with synthesized netlist generation using automated simulation-based verification [3]. A faster verification architecture is required with the early checks to encounter bugs before physical implementation. The ESL design and verification is currently an important field of research.
This paper presents Universal Verification Methodology (UVM) testbench architecture which supports stimulus-based functional verification and power-aware verification at multiple levels of abstraction. The proposed testbench flow accelerates the design verification and improves the coverage closure. It also directs the automated power checks and power-state coverage data collection with the power management reporting mechanism. Dynamic power is due to the continual toggling of power-consuming clocks between ‘on’ and ‘off’ states. When the SoC is off, it should not draw any current, but there is a continuous current due to source-drain reverse bias diffusion and inversion current under threshold voltage at the gate. The power consumed by this leakage current is called static leakage power. Static power is categorized as leakage and standby. Standby power consumption is a continuous consumption from VDD to ground. As the size of the device reduces, static leakage power becomes more critical. Static leakage power is the chief concern in the verification of active power management. The power management is done in the later phases of the design cycle because power specification libraries do not support high-level languages like SystemVerilog and UVM. There are very few approaches working on early-stage power-aware verification. SystemC power gating technique uses specific class data types and clock synchronization as defined in conventional work [4]. The other early power-aware verification advancement is through pin-signal driven power architectures using UPF 1.0 with precise cycle-accurate SystemC design models [5]. SystemC modeling offers a crucial trade-off between speed and accuracy.
It is essential to consider power throughout the design process with concurrent verification and equivalence checking [6]. It is best to design and verify power management upfront because of the maximum available flexibility to exert the impactful leverage on the result. The system abstraction level and architectural design flow are shown in Fig. 1. The higher the abstraction level, the higher the flexibility. The ESL level golden macro-architecture gives an edge over RTL level micro-architecture to catch design issues earlier. Graphic Design System II (GDSII) layout is the final product of the SoC design cycle for IC fabrication at physical level of abstraction.
The proposed verification architecture supports active power management, TLM stimulus-based functional verification, automated register abstraction verification and automated coverage and power checks, as shown in Fig. 2. The testbench architecture attains the following objectives of power-aware management and functional verification intent:
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Simulations of power-aware management UPF architecture using ESL abstraction for early verification. Visualization of failure, isolation or retention. Automatic power checks for power management errors.
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Addition of transaction-level modeling based stimulus generation in testbench for functional verification of design with assertion based self-checking mechanism [7].
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Automated register abstraction layer implementation on testbench for register power-aware verification.
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Collection of power states, transition coverage and functional coverage with automated coverage [8] and power checks.
The existing methods related to the register database abstraction and ESL power-aware verification are discussed in Sec. 2. The proposed testbench architecture of register abstract behavior database creation with ESL power-aware management verification flow is analyzed in Sec. 3.1 Automated register access, 3.2 Active power-aware simulation verification flow. This paper proposes two different paths for verification: frontdoor and backdoor. Frontdoor path provides greater flexibility and functional coverage but is relatively slower as compared to backdoor path. We have proposed algorithm 1 to select the minimum test path among the similar test paths using MINIMIN search and α-trimming function is explained in Sec 3.3. Sec. 4 explains the case study of three and five power domains to test the results. This experimentation identifies that for small designs, the proposed architecture is not as precise as it is for big SoCs. The ESL simulation, ESL power model generation and power error estimation on 20 power domain SoC ©NXP Semiconductors is discussed in Sec. 5. The experiment results supporting the benefits of the contribution are discussed in Sec. 6. Sec. 7 concludes this paper.
Section snippets
Related work
There are several works and methodologies for SoC verification using UPF for power management. The IEEE introduced regular updation strategies for power management in 2009 [9]. The power intent is useless when defined at later stages of design development. The concept is that if the specification changes at later stages, the power intent also needs modification according to the design alteration. If power intent is dependent on the application then it always requires a change after change in
Proposed automated register access power-aware testbench architecture
The proposed architecture is a combination of automated register abstraction and power-aware verification techniques, as shown in Fig. 3. The testbench architecture also supports the TLM based automated coverage mechanism [8,16]. The UVM register model allows the stimulus and transactions as a protocol-independent register layer on top of any verification environment [8,23,24]. The testbench architecture concurrently performs the verification of design, design registers and power management as
Case studies
The low power mixed-signal three power domain design is shown in Fig. 11. The PD2 is the high-performance domain with multiple cores and on-chip flash. PD1 is a low power subsystem consisting of a lightweight core and analog/digital peripherals. PD0 is an always ‘on’ domain having a complex power management monitoring unit. There are multiple pads in the design to associate with switchable power domains as well as with the always ‘on’ domain in the design. The design supports various low power
ESL power-aware simulation
ESL is the formal description of the complete system. The abstraction is at block-level while the functional description is made in high-level language. The timing information is explained in the program code. This enables the way to execute the initial abstracted specifications of the complete design at the system level. This total system is called Virtual Platform (VP). The virtual platform works as a ESL level simulator. We have used these virtual platforms to simulate several benchmarks and
Results and discussions
This section provides multiple results to support the benefits of the experiment. The initial outcome shows mean handle access to every module of INX2091. The ESL mean handle gets early access over RTL to execute faster simulation (Fig. 18, Fig. 19 and Table 2). The next part compares Case I and II (three and five power domain design blocks) to elucidate the fact that the proposed architecture doesn't possess any merit when it is used over fewer power domains because of automation and
Conclusion
The power-aware verification methods are of top concern for many industries to improve verification productivity. The proposed ESL register abstraction power-aware UVM testbench upstages the conventional RTL-level power verification. The improvement is in terms of the number of required module handle, CPU processing time, simulation time and power/functional coverage matrices. The results show 11.01% and 17.65% improvement in terms of CPU processing time and simulation time respectively with 16
Authorship contributions
Category 1: Conception and design of study: Gaurav Sharma, Lava Bhargava, Vinod Kumar. acquisition of data: Gaurav Sharma, Lava Bhargava. analysis and/or interpretation of data: Gaurav Sharma, Lava Bhargava. Category 2: Drafting the manuscript: Gaurav Sharma, Lava Bhargava. revising the manuscript critically for important intellectual content: Gaurav Sharma, Lava Bhargava, Vinod Kumar. Category 3: Approval of the version of the manuscript to be published (the names of all authors must be
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgment
This work is supported by the Ministry of Electronics and Information Technology, Government of India under grant number VISPHD-MEITY-1498.
References (34)
- et al.
Simplifying low-power soc top-down design using the system-level abstraction and the increased automation
Integrat. VLSI J.
(2018) - et al.
System-level modeling of energy in TLM for early validation of power and thermal management
- et al.
Power domain management interface: flexible protocol interface for transaction-level power domain management
IET Comput. Digital Tech.
(July 2013) - et al.
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing
(2012) - et al.
Automated simulation-based verification of power requirements for systems-on-chips
- et al.
Formal verification of architectural power intent
IEEE Trans. Very Large Scale Integr. Syst.
(Jan 2013) - et al.
Synthesis of system verilog assertions
- et al.
A novel and robust implementation of register abstraction on uvm testbench
Int. J. Simulat. Syst. Sci. Technol.
(Feb 2018) Ieee standard for design and verification of low-power, energy-aware electronic systems
IEEE Std
(March 2019)- et al.
Successive refinement: a methodology for incremental specification of power intent
Refining successive refinement: improving a methodology for incremental specification of power intent
SynopsysⓇ low-power flow user guide
Unified power format (upf) methodology in a vendor independent flow
Formal verification of hardware/ software power management strategies
Verification of power-management specification at early stages of power-constrained systems design
J. Circ. Syst. Comput.
Automated coverage register access technology on uvm framework for advanced verification
Energy efficient implementation, power aware simulation and verification of 16-bit alu using unified power format standards
Cited by (1)
A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs
2022, Microelectronics ReliabilityCitation Excerpt :The work in [21] describes the significance of the C test random stimulus to acquire the register configuration in the stipulated time frame. The paper [22] explained the power aware coverage oriented verification structure to create an unbiased stimulus reuse at TLM. The SystemC compilation, simulation, and performance issues are addressable with the use of an appropriate stimulus generation approach.