1 Introduction

Interesting features such as high photodetection efficiency, robustness, high gain and low-cost has created a high interest in Silicon Photomultiplier detectors (SiPM), which are very promising in different fields of fast timing applications such as medical imaging (TOF-PET) and high energy physics [1,2,3,4,5,6]. On the other side, SiPMs have drawbacks related to some performance parameters for the dedicated preamplifier. For example, to avoid the reduction in response time caused by high value output capacitance of SiPM, (which exhibits values in the range of hundreds of pF [7, 8]), the preamplifier circuit must exhibit very low input impedance. In addition, SiPMs do not behave as an ideal current source and their equivalent output impedance varies by the amount of incident light. Therefore, the low input impedance of the preamplifier is mandatory to keep the nonlinear behavior caused by non-constant output impedance of SiPM, as low as possible. Another important parameter of preamplifier is the low noise performance which is crucial to avoid whole system signal-to-noise degradation. Definitively, as the amplitude of SiPM output current is low, the preamplifier should exhibit very low noise feature. Finally, in order to use the full potential of SiPM in achieving fast response time, high frequency performance is another critical parameter in the associated preamplifier. The reduction in the allowed supply voltage in advanced CMOS technologies also puts severe limitations on the preamplifier dynamic range. All these considerations reveal that the design of preamplifier circuit for SiPM is very challenging because there is a need for a careful optimization of trade-offs between input impedance, bandwidth, dynamic range, noise performance and power consumption. Therefore, novel circuit topologies should be developed to relax the downsides of SiPM and fully exploit its desired features.

Recently, with the aim of designing a very effective SiPM preamplifier circuit, a new approach based on second generation voltage conveyor (VCII) has been introduced and its effectiveness has been investigated in literature [9,10,11,12,13,14]. Especially in [13] a comparative analysis on realizing various analog functions using VCII, CCII and operational amplifiers is given. Figure 1(a) reports the symbol of VCII, which is the dual of well-known second generation current conveyor (CCII) [12,13,14]. Unlike CCII, VCII Y node is a low impedance current input port. The impedance at Y node is ideally zero, so it can be used as preamplifier input. X is a high impedance current output or voltage input terminal. The input current at Y node is transferred to X node by a current gain ± β very close to unity. VCII+ and VCII− are denoted by + β and –β respectively. The Z terminal is a low impedance voltage output node. The voltage produced at X terminal is transferred to Z terminal by a voltage gain α ideally close to unity:

$$\beta =\frac{{\beta }_{0}}{1+\frac{s}{{P}_{\beta }}} , \alpha =\frac{{\alpha }_{0}}{1+\frac{s}{{P}_{\alpha }}}$$
(1)

being β0 and α0 DC gain values and Pβ and Pα the  − 3 dB bandwidths of β and α respectively. The operation of VCII based SiPM preamplifier in a transimpedance amplifier (TIA) configuration [10], shown in Fig. 1(b), can be simply explained as follows. The SiPM is connected to the low impedance Y port of VCII. The output current of SiPM entering Y port is transferred to X terminal with a gain close to unity. A gain controlling resistor Rg is connected to X terminal. Therefore, the current inside X terminal of SiPM is transferred to a proportional voltage at X node, then the produced voltage is transferred to Z port. Using Eq. (1) the output voltage is found as:

$${V}_{out}\approx \pm \frac{{\beta }_{0}{\alpha }_{0}{R}_{g}}{(1+\frac{s}{{P}_{\beta }})(1+\frac{s}{{P}_{\alpha }})(1+s{R}_{g}{C}_{x})} {I}_{d}$$
(2)

being Cx the total parasitic capacitance at X terminal. By assuming Pβ, \({P}_{\alpha }\) > > (RgCx)−1, Eq. (2) is simplified to:

Fig. 1
figure 1

VCII a Symbolic representation [12] and b SiPM preamplifier [10]

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$${V}_{out}\approx \pm \frac{{\beta }_{0}{\alpha }_{0}{R}_{g}}{(1+s{R}_{g}{C}_{x})} {I}_{d}$$
(3)

From Eq. (3), it is found that the bandwidth is determined by the gain controlling resistor Rg and parasitic capacitance at X terminal.

Using VCII based approach to implement SiPM preamplifier, the following benefits are achieved:

  1. (1)

    The inherent low input impedance at Y port is very effective in mitigating the effect of SiPM parasitic impedance and capacitance effects.

  2. (2)

    Thanks to the current mode operation, the bandwidth and dynamic range are high.

  3. (3)

    The bandwidth is high because is mainly determined by gain setting resistor Rg and the parasitic capacitance at X terminal. Therefore, high bandwidth is simply achievable by reducing Cx through a proper circuit design.

In the previously published works [9,10,11], the response time and frequency performance of VCII based SiPM preamplifier have been investigated. Since the noise is also a very important parameter, in this paper we address the noise performance of a VCII based preamplifier. As VCII is the dual circuit of CCII, for noise calculations, we follow the approach for current conveyor noise analysis presented in [15]. We start by introducing noise sources in VCII block. Using this model, we derive the output equivalent noise of a general VCII based SiPM preamplifier circuit. Then the noise calculations of VCII CMOS implementation are presented. Based on the results of this study, methods to achieve lower noise performance are discussed. The formulas of the preamplifier key parameters including the VCII node impedances and bandwidth are derived. To confirm the presented theory, Spice simulate results are performed. They show that by applying the discussed optimization methods, the noise performance is significantly improved when compared to the previously designed VCII based preamplifier while preserving other parameter values (voltage and current gains, bandwidth and parasitic impedances). The organization of this paper is as follows: In section II, noise model of VCII is introduced and based on this model the output noise of VCII based SiPM preamplifier is established. In Sect. 3, the CMOS implementation of VCII and its performance parameters are given. Then, the equivalent noises at its different ports are analyzed. The trade-offs existing between other performance parameters and noise parameter are discussed. Finally, in Sect. 4 simulation results are provided.

2 Noise analysis of a VCII based SiPM preamplifier

2.1 Noise sources of VCII block and VCII based SiPM preamplifier

Figure 2 shows the noise model of VCII block. Similar to current conveyors [16], VCII is a multiple-port device where each terminal is represented by an equivalent voltage noise and an equivalent current noise. As it will be shown, for a specific application not all but some of the noise sources play more important role compared to other noise sources. This fact simplifies the designer task to consider those critical noise sources in the circuit design. Figure 3 shows the VCII based SiPM preamplifier noise model (being Zpar the equivalent impedance resulted from parallel connection of Cpar and Rpar). In this application, Y port is connected directly to the SiPM which exhibits high output impedance; therefore, the contribution of Y port equivalent noise voltage to the overall noise performance is negligible. In other words, due to high output impedance of SiPM the current noise produced by dv2Yneq is unimportant; therefore, its effect can be neglected. Due to current buffering action between Y and X ports and voltage buffering action between X and Z ports, any current noise source at Y port is transferred to X port and any noise voltage at X port is transferred to Z port. Assuming unity value for α and β, the output noise voltage of Fig. 3 is calculated as:

Fig. 2
figure 2

Noise model of VCII

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Fig. 3
figure 3

Noise model of VCII based SiPM preamplifier

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$$\overline{d{v}_{out}^{2}}=\left(\overline{d{i}_{Yneq}^{2}}+\overline{d{i}_{Xneq}^{2}}\right){R}_{g}^{2}+\overline{{dv}_{Xneq}^{2}}+\overline{{dv}_{Rg}^{2}}+\overline{{dv}_{Zneq}^{2}}+\overline{d{i}_{Zneq}^{2}}{R}_{L}^{2}+\overline{{dv}_{RL}^{2}}$$
(4)

The two thermal noise contributions of Rg and RL are respectively: \(\overline{{dv}_{Rg}^{2}}=4kT{R}_{g}df\) and \(\overline{{dv}_{RL}^{2}}=4kT{R}_{L}df\), where k is Boltzmann constant, T is absolute temperature, df is frequency bandwidth. In Eq. (4), it is assumed that Rg <  < RX and RZ <  < RL.

2.2 Noise calculation of VCII circuit

For noise analysis we consider the VCII CMOS implementation of Fig. 4 which has been used in [10] to implement a SiPM preamplifier. In this circuit the negative feedback loop established by differential pair M1-M4 is used to reduce the impedance at Y port and to clamp VY at ground. The current at Y port is transferred to X port by means of simple current mirror made of M6-M7. The voltage produced at X port is transferred to Z port through a simple flipped voltage follower (FVF) [17] based voltage buffer made of M9-M10.

Fig. 4
figure 4

CMOS implementation of VCII [10]

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M8 is used to set the DC offset voltage at Z port equal to zero. The small signal equivalent circuit of Fig. 4 is shown in Fig. 5 where, roi and gmi denotes the output impedance and transconductance of related transistor. Also, roIBi denotes the output impedance of related current source. Using the presented small signal model, the simplified formulas of impedances at Y, X and Z ports as well as those for α0 and β0 are expressed as respectively:

Fig. 5
figure 5

Small signal equivalent circuit of Fig. 4

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$${r}_{y}\approx {\left[{gm}_{2}{gm}_{5}{\bullet (ro}_{2}//{ro}_{4})\right]}^{-1}$$
(5)
$${r}_{x}\approx {ro}_{IB3}//{ro}_{7}$$
(6)
$${r}_{Z}\approx {\left[{gm}_{9}{gm}_{10}{ro}_{IB4}\right]}^{-1}$$
(7)
$${\alpha }_{0}\approx \frac{{ro}_{7}}{{ro}_{7}+{gm}_{8}^{-1}}$$
(8)
$${\beta }_{0}\approx \frac{{gm}_{7}}{{gm}_{6}}$$
(9)

In Eq. (5), pair wise matching between differential pair transistors is assumed.

Figure 6 shows the noise model of VCII circuit of Fig. 4 where the noise produced by each MOS transistor is presented as a current source connected in parallel to it. For proper noise calculation, in Fig. 6, the implementation of current sources IB1–IB4 by means of simple current mirrors are also shown. The transistor noise includes 1/f and channel thermal noise.

Fig. 6
figure 6

VCII CMOS circuit with noise sources

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The contribution of 1/f noise on the overall wide bandwidth noise is negligible, therefore the output current noise of the ith transistor is approximated as thermal noise [16]:

$$\overline{d{i}_{ni}^{2}}=4kT\gamma {gm}_{i}df$$
(10)

where k is Boltzmann's constant, T is absolute temperature, df is frequency bandwidth, γ is a constant coefficient ranging from 1/3 to 2/3 and gmi is the transconductance of the ith transistor.

The noise contribution of differential pair made of M1-M4 is a noise voltage at Y port expressed as:

$$\left.\overline{d{v}_{M1-M4}^{2}}\right|at Y\approx 4\frac{\overline{d{i}_{n1}^{2}}+\overline{d{i}_{n2}^{2}}+\overline{d{i}_{n3}^{2}}+\overline{d{i}_{n4}^{2}}}{{{g}_{m}}^{2}}$$
(11)

being \({g}_{m1}={g}_{m2}={g}_{m}\).

The noise contribution of current source IB1 is negligible. The reason is that the output noise produced by IB1 is attenuated by differential pair as a common mode signal. Transistor M5 also produces noise voltage at Y port equal to:

$$\left.\overline{d{v}_{M5}^{2}}\right|at Y=\frac{\overline{d{i}_{n5}^{2}}}{{{g}_{m5}}^{2}{{g}_{m}}^{2}{({r}_{o2}\Vert {r}_{o4})}^{2} }$$
(12)

Using Eq. (11) and Eq. (12), the total noise voltage at Y port is:

$$\overline{d{v}_{yneq}^{2}}=\left.\overline{d{v}_{M1-M4}^{2}}\right|at Y+\left.\overline{d{v}_{M5}^{2}}\right|at Y\approx \frac{4kT\gamma }{g{m}_{1}^{2}}\left[{4gm}_{1}+4g{m}_{2}+4{gm}_{3}+{4gm}_{4}+\frac{1}{{g}_{m5}{({r}_{o2}\Vert {r}_{o4})}^{2} }\right]df$$
(13)

From Eq. (13), it is seen that increasing gm2 reduces the equivalent current noise voltage at Y port. From Eq. (5), the impedance at Y terminal is also improved by increasing gm2.

Considering the relationship between bias current and overdrive voltage with gm2 represented in Eq. (14), reveals that the allowed supply voltage and the required power consumption set a limit on the maximum value of gm2, because increasing gm2 demands high value for IB2 and consequently the high value of overdrive voltage VGS2-VTH is required to keep M1-M4 in saturation region. Equation (14) shows also the well-known alternative representation of gm2 in terms of transistor aspect ratios and bias currents in strong inversion. After setting the value of IB1 based on circuit power budget, the value of gm2 can be increased by selecting large values for M1-M2 aspect ratios. By this, although the parasitic capacitance associated with Y port will increase, but due to the concurrent reduction in Y port impedance, the effect of increasing aspect ratio of M1-M2 on the frequency performance will be negligible. It is worth mentioning that the transistors size increase must not push them in weak inversion region:

$${gm}_{2}=\frac{2{I}_{B1}}{{V}_{GS2-}{V}_{TH2}}=\sqrt{{{I}_{B1}\mu }_{n}{C}_{ox}\frac{{W}_{2}}{{L}_{2}}}$$
(14)

The noise contribution of M5 is a voltage at Y port equal to:

$$\overline{d{v}_{M5}^{2}}=\frac{\overline{d{i}_{n5}^{2}}}{{A}^{2}{g}_{m5}^{2}}=\frac{4kT\gamma df}{{A}^{2}{g}_{m5}}$$
(15)

where, by assuming pair wise matching between differential amplifier transistors (i.e. M1 to M2 and M3 to M4), A is:

$$A\approx {g}_{m}({ro}_{4}\Vert {ro}_{2})$$
(16)

being gm the transconductance of M1-M2. According to Eq. (15) and Eq. (16), to reduce the noise contribution of M5, its gm value should be high. It is remarkable that the noise voltage at Y node does not contribute to the total output noise of the TIA (see Eq. (4)).

The equivalent current noise at Y port is expressed as:

$$\overline{d{i}_{Yneq}^{2}}=\overline{d{i}_{n6}^{2}}+\overline{d{i}_{nIB2}^{2}}=\overline{d{i}_{n6}^{2}}+\overline{d{i}_{nMB2}^{2}}+\overline{d{i}_{nMB0}^{2}}=4kT\gamma ({gm}_{6}{+gm}_{B2}{+gm}_{B0})df$$
(17)

As M6 is a PMOS transistor, its produced channel noise is lower. It is also worth mentioning that as there is good matching between transistors with large aspect ratios [18, 19], according to Eq. (9), to keep the value of β0 at unity, large aspect ratios must be set for M6-M7. This will increase the parasitic capacitances associated with these transistors. However, as the input impedance of current mirror M6-M7 will reduce by increasing their aspect ratios, the effect on overall bandwidth will be partly compensated. In addition, referring to Eq. (8), to keep the α0 close to unity, large value is required for ro7 which can be set by increasing channel length or reducing its bias current. However, the required dynamic range sets a limit on the minimum value of bias current. The noise produced by current source IB2 can be made negligible by setting the gm of the related transistors as low as possible.

The equivalent current noise at X port is:

$$\overline{d{i}_{Xneq}^{2}}=\overline{d{i}_{n7}^{2}}+\overline{d{i}_{nIB3}^{2}}=\overline{d{i}_{n7}^{2}}+\overline{d{i}_{nMB3}^{2}}+\overline{d{i}_{nMB0}^{2}}=4kT\gamma \left({gm}_{7}+{gm}_{B3}+{gm}_{B0}\right)df$$
(18)

Similar considerations can be done for this result.

The equivalent voltage noise at X port is also obtained as:

$$\overline{d{v}_{Xneq}^{2}}=\frac{\overline{d{i}_{n8}^{2}}}{{gm}_{8}^{2}}+\frac{\overline{d{i}_{n9}^{2}}}{{gm}_{9}^{2}}==4kT\gamma ({{gm}_{8}}^{-1}+{{gm}_{9}}^{-1})df$$
(19)

As Eq. (19) implies, choosing large values for gm8 and gm9, the noise voltage at X terminal is reduced. In the circuit of Fig. 6, the same noise voltage at X node is produced at Z terminal.

The expression for noise current at Z port is:

$$\overline{d{i}_{Zneq}^{2}}=\overline{d{i}_{n10}^{2}}+\overline{d{i}_{nIB4}^{2}}=\overline{d{i}_{n10}^{2}}+\overline{d{i}_{nMB4}^{2}}+\overline{d{i}_{nMB5}^{2}}= 4kT\gamma {(gm}_{10}+{gm}_{B4}+{gm}_{B5})df$$
(20)

As the MB4-MB5 are PMOS transistors which inherently produce low noise compared to NMOS transistors, the effective method to reduce current noise at Z output is reducing the value of gm10. To avoid increasing the impedance at Z port due to the reduction of gm10, the output impedance of IB3 current source should be increased by choosing large values for the channel length of transistor MB4-MB5.

3 Simulations

The VCII circuit of Fig. 4 is simulated using Spice and 0.35 µm CMOS technology with a supply voltage of ± 1.65 V. The approach we used to optimize noise performances is given in Table 1. Table 2 shows the new values for transistors’ aspect ratios along with the former ones from [10]. A comparison between pre and post optimization VCIIs is given in Table 3 where noise sources at Y, X and Z ports as well as other performance parameters are given.

Table 1 Noise reduction cause-effect table
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Table 2 Transistors aspect ratio and current source values of the VCII before [10] and after optimization
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Table 3 Performance and noise parameters of the VCII (Left) and open loaded TIA (Right) before [10] and after optimization
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As it is stated in Table 2, the major increase in aspect ratio is equal to 10 times related to M1-M2 and M5, so we expect approximately 30% increase in the used area. However, investigating the achieved noise results at Table 3 shows a 51 times reduction for noise current at Y node, a 121 times reduction for noise current at X, a 105 times reduction for noise voltage at X, a 58 times reduction for noise current at Z and a 107 times reduction for noise voltage at Z while the increase in power consumption is only 52 μW and other performance parameters remain rather unchanged. We added these points in the simulation results.

The output noise of the VCII based preamplifier (Fig. 1b), expressed by Eq. (4) is shown in Fig. 7 after and before optimization. As it is seen, in agreement with Table 3, it is reduced from 3.2 µV/√Hz to 29.9 nV/√Hz (@100 kHz) in the optimized circuit. The frequency performance of VCII-based preamplifier for different values of Rg is also shown in Fig. 8. As it is seen, the applied optimization does not have significant effect on the frequency performance.

Fig. 7
figure 7

The output noise of the VCII based preamplifier after and before optimization

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Fig. 8
figure 8

The frequency performance of the VCII based preamplifier after and before optimization

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4 Conclusions

In this paper we address the noise model and performance of VCII-based SiPM preamplifier. As a multi-port device, each port is modeled by an equivalent voltage and current noise. It is discussed that due to the high output impedance of SiPM, the equivalent noise voltage at Y port does not contribute to the overall noise performance of VCII based preamplifier. However, both equivalent current and voltage noises at X port are transferred to the output and play an important role on the determining noise at preamplifier output port.