Skip to main content
SpringerLink
Log in

Design and Analysis of a Dual-Metal-Implanted Triple-Material Cylindrical Gate-All-Around Nanowire FET with Negative Differential Resistance and Negative Transconductance Behaviors

  • Original Research Article
  • Published:
Journal of Electronic Materials Aims and scope Submit manuscript

Abstract

In this paper, we introduce three new structures of a cylindrical gate-all-around nanowire (NW) field-effect transistor (FET) to achieve negative differential resistance (NDR) and negative transconductance (NTC) behaviors. In the first structure, only one metal is implanted in the channel near the drain of the dual-material cylindrical gate-all-around NWFET based on the energy band profile modulation to obtain the NDR behavior. To achieve NTC behavior, another metal is implanted in the channel near the source; therefore, the second structure has both the NDR and NTC behaviors. In the final structure, the use of a triple-metal gate is proposed to improve the peak-to-valley current ratio. The NTC behavior occurs when the increase in VGS creates a positive lateral electric field in the channel, which causes the potential barrier tunneling (PBT) to decrease. The cause of the positive electric field formation is the cavity in the channel’s potential barrier due to implanted metals. Furthermore, by increasing VDS, the high electron scattering caused by the high electric field at the beginning of the drain region is increased and causes the electron drift velocity and IDS to decrease. Consequently, the NDR behavior is achieved. The structures are carefully simulated using numerical simulation based on non-local tunneling, and also the transfer characteristics (IDS − VGS) and the output characteristics (IDS − VDS) are attentively analyzed and examined.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. T. Li, X. Li, M. Tian, Q. Hu, X. Wang, S. Li, and Y. Wu, Nanoscale 11, 4701 (2019).

    Article  CAS  Google Scholar 

  2. H. Yoo, S. On, S.B. Lee, K. Cho, and J.J. Kim, Adv. Mater. 31, 1808265 (2019).

    Article  Google Scholar 

  3. S. Karmakar, Novel Three-State Quantum Dot Gate Field Effect Transistor (Berlin: Springer, 2014), pp. 1–4.

    Book  Google Scholar 

  4. Z. Xiao, C. Ma, J. Huang, L. Liang, W. Lu, K. Hong, B.G. Sumpter, A.P. Li, and J. Bernholc, Adv. Theory Simul. 2, 1800172 (2019).

    Article  Google Scholar 

  5. E. Ko, J. Shin, and C. Shin, Nano Converg. 5, 1 (2018).

    Article  Google Scholar 

  6. Y. Liu, J. Guo, Q. He, H. Wu, H.-C. Cheng, M. Ding, I. Shakir, V. Gambin, Y. Huang, and X. Duan, Nano Lett. 17, 5495 (2017).

    Article  CAS  Google Scholar 

  7. A. Manjanath, A. Roy, A. Samanta, and A.K. Singh, Nanotechnology 28, 275402 (2017).

    Article  Google Scholar 

  8. V. KhademHosseini, D. Dideban, M.T. Ahmadi, R. Ismail, and A.E.U. Int, J. Electron. Commun. 90, 97 (2018).

    Google Scholar 

  9. H. Mohammadpour, Physica E Low Dimens. Syst. Nanostruct. 81, 91 (2016).

    Article  CAS  Google Scholar 

  10. J. Yun, H. An, R. Huang, M. Guo, Y. Zhang, and P. Kang, IEEE Trans. Electron Dev. 67, 2529 (2020).

    Article  CAS  Google Scholar 

  11. R.M.I. Abadi and M. Saremi, J. Electron. Mater. 47, 1091 (2018).

    Article  Google Scholar 

  12. F. Salimian and D. Dideban, Phys. E Low Dimens. Syst. Nanostruct. 104, 268 (2018).

    Article  CAS  Google Scholar 

  13. M. Vali, D. Dideban, and N. Moezi, Superlattices Microstruct. 100, 1256 (2016).

    Article  CAS  Google Scholar 

  14. S.A. Sedigh Ziabari and M.J. Tavakoli Saravani, Int. J. Nano Dimens. 8, 107 (2017).

    Google Scholar 

  15. A. Bozorgi Golafzani and S.A. Sedigh Ziabari, Int. J. Nano Dimens. 11, 12 (2020).

    Google Scholar 

  16. J.W. Lee and W.Y. Choi, Solid State Electron. 163, 107659 (2020).

    Article  Google Scholar 

  17. F. Salimian, D. Dideban, and A.E.U. Int, J. Electron. Commun. 110, 152841 (2019).

    Google Scholar 

  18. F.Y. Niyat and S.E. Hosseini, Phys. E Low Dimens. Syst. Nanostruct. 114110 (2020).

  19. R. Hosseini, M. Fathipour, and R. Faez, Int. J. Electron. 99, 1299 (2012).

    Article  CAS  Google Scholar 

  20. Atlas User’s Manual. (Silvaco Inc., 2016).

  21. R.M.I. Abadi and S.A.S. Ziabari, Appl. Phys. A Mater. Sci. Process. 122, 988 (2016).

    Article  Google Scholar 

  22. M. Abedini, S.A.S. Ziabari, and A. Eskandarian, Int. Nano Lett. 8, 277 (2018).

    Article  CAS  Google Scholar 

  23. B. Ghosh, P. Bal, and P. Mondal, J. Comput. Electron. 12, 428 (2013).

    Article  CAS  Google Scholar 

  24. J. Patel, D. Sharma, S. Yadav, A. Lemtur, and P. Suman, Microelectron. J. 85, 72 (2019).

    Article  CAS  Google Scholar 

  25. N. Kumar, U. Mushtaq, S.I. Amin, and S. Anand, Superlattices Microstruct. 125, 356 (2019).

    Article  CAS  Google Scholar 

  26. S. Sahay and M.J. Kumar, Junctionless Field-Effect transistors: Design, Modeling, and Simulation (New York: Wiley, 2019), pp. 28–31.

    Book  Google Scholar 

  27. Z. Jiang, Y. Zhuang, C. Li, and P. Wang, J. Electron. Mater. 46, 1088 (2017).

    Article  CAS  Google Scholar 

  28. B. Streetman and S. Banerjee, Solid State Electronic Devices, Global ed. (London: Pearson Education Limited, 2015), pp. 251–258.

    Google Scholar 

  29. S.S. Li, Semiconductor Physical Electronics (New York: Springer, 2012), pp. 252–284.

    Google Scholar 

  30. P. Zhang, S.T. Le, X. Hou, A. Zaslavsky, D.E. Perea, S.A. Dayeh, and S.T. Picraux, Appl. Phys. Lett. 105, 062106 (2014).

    Article  Google Scholar 

  31. S. Yadav, M. Vemulapaty, D. Sharma, A. Gedam, and N. Sharma, Micro Nano Lett. 14, 450 (2019).

    Article  CAS  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran

    Sadra Sadeghpoor Ajibisheh, Seyed Ali Sedigh Ziabari & Azadeh Kiani-Sarkaleh

Authors
  1. Sadra Sadeghpoor Ajibisheh
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Seyed Ali Sedigh Ziabari
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Azadeh Kiani-Sarkaleh
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

All authors designed new structures and analyzed simulation data. All authors contributed to the writing, editing, and approval of the paper.

Corresponding author

Correspondence to Seyed Ali Sedigh Ziabari.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sadeghpoor Ajibisheh, S., Sedigh Ziabari, S.A. & Kiani-Sarkaleh, A. Design and Analysis of a Dual-Metal-Implanted Triple-Material Cylindrical Gate-All-Around Nanowire FET with Negative Differential Resistance and Negative Transconductance Behaviors. J. Electron. Mater. 50, 170–185 (2021). https://doi.org/10.1007/s11664-020-08572-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11664-020-08572-2

Keywords

Search

Navigation