Legacy software migration based on timing contract aware real-time execution environments

https://doi.org/10.1016/j.jss.2020.110849Get rights and content

Highlights

  • Propose a timing-aware legacy software migration solution.

  • Provide a set of portable temporal construct to enforce legacy timing behaviour.

  • Integrate the temporal construct within a machine-adaptable static binary translator.

  • Validate legacy timing behaviour on the new HW using formal timing specifications.

Abstract

The evolution to next generation embedded systems is shortening the obsolescence period of the underlying hardware. As this happens, software designed for those platforms (a.k.a., legacy code), that might be functionally correct and validated code, may be lost in the architecture and peripheral change unless a retargeting approach is applied. Embedded systems often have real-time computing constraints, therefore, the legacy code retargeting issue directly affects real-time systems. When dealing with real-time legacy code migration, the timing as well as the functional behaviour must be preserved. This article sets the focus on the timing issue, providing a migration path to real-time legacy embedded control applications by integrating a portable timing enforcement mechanism into a machine-adaptable binary translation tool. The proposed timing enforcement solution provides at the same time means for validating the legacy timing behaviour on the new hardware platform using formal timing specifications in the form of contracts.

Introduction

Companies within the embedded systems industry are facing a relentless demand for increasingly stringent requirements such as better performance, increased dependability, and energy efficiency, while offering a cost-effective product within a reduced time-to-market. This transition to next generation embedded systems is being encouraged by the rapid development of computing architectures. As a consequence, the obsolescence period of embedded systems is being shortened and there is a need to deal with legacy systems and their integration.

Legacy systems are characterized by some particular properties:

  • Usually runs on obsolete hardware which is slow and expensive to maintain (Wu et al., 1997).

  • Use customized and deprecated toolchain(s) (Wagner, 2014).

  • Have no or outdated documentation and original developers or users are no longer available (Wagner, 2014).

  • Are essential for the company (Bennett, 1995) since they comprise business knowledge (Wahler et al., 2015).

Due to their nature and particular properties, legacy systems present a complex scenario in software maintenance and evolution. Hence, the process of updating legacy systems is usually complex, error-prone, time-consuming and requires high cost investment.

Binary translation appears to be a standard approach when it comes to legacy software migration, since the binary that runs on the legacy hardware can be ported to a new hardware platform without a considerable expense of time, effort and money. Software recompilation is also a well known approach to port platform-independent legacy source code.

However, when dealing with Real-Time (RT) legacy code migration, not just the functional behaviour, but also the timing behaviour must be preserved. To the authors knowledge, limited solutions exist to port real-time legacy software, while existing solutions have limitations regarding their portability. Therefore, industry still needs a low-overhead embedded RT legacy software retargeting solution that can be easily ported to different source and target architectures.

In the direction to solve this problem, this work sets the focus on the timing issue, therefore, the overall goal of this research is to provide a migration path to real-time legacy embedded control applications by integrating a portable timing enforcement mechanism into a machine-adaptable binary translation tool. The proposed solution should also provide means to validate the legacy timing behaviour on the new hardware platform.

As a first step on this research, Yarza et al. (2020) studies the feasibility of two machine-adaptable binary translators, one dynamic and the other one static, for their use in a RT property conserving legacy software migration process. Based on these translation tools, two (dynamic and static) RT legacy source code migration solutions are proposed. The feasibility study compares the measured execution time of a set of Worst Case Execution Time (WCET) representative benchmarks running on the legacy and new hardware platforms using both migration approaches. From this feasibility study, the static approach is selected to implement a timing contract aware real-time legacy software migration solution, since it provides a more deterministic timing behaviour and less translation overhead. The main contribution of this article are:

  • The systematic annotation of legacy timing properties into the behavioural legacy source code using a set of portable temporal construct that provide means to enforce a specific timing behaviour within the legacy software.

  • The systematic transformation of legacy timing properties into formal timing specifications for their latter use within the timing validation phase.

  • The integration of the temporal constructs within the binary translation process to achieve a timing-aware legacy software migration.

The remainder of this paper is organized as follows. An overview of related work in the area of timing-aware recompilation and machine-adaptable binary translation techniques is provided in Section 2. Then, in Section 3 the proposed migration path is constraint to a specific class of application. Then, based on these constraints, Section 6 presents the RT legacy software migration path. The proposed solution is then assessed in Section 7 and obtained results are analysed. Finally, Section 8 gives a conclusion and outlook on future work.

Section snippets

Related work

Given that legacy software migration is a common issue in industry, it has been widely studied during the last decades. However, when porting RT legacy software, not just the functional behaviour, but also the timing behaviour must be preserved. This section provides an overview of existing solutions for a timing-aware recompilation of legacy C source code, as well as binary translation tools targeting either a machine-adaptable or a RT legacy code migration solution. The related work

Real-time legacy system model definition

The RT legacy control system is a computer system that executes a set of periodic tasks according to a predefined static scheduling policy. The following subsections describe through formal notation the main modelling elements in the considered RT legacy system.

Time measurement & control blocks

A timing-aware migration requires means to first extract and then enforce the legacy timing properties. Time measurement and control blocks aid this process, the time measurement block is used to extract the legacy timing behaviour and the time control blocks are used to enforce this timing behaviour on the new platform. The proposed time measurement and control solution is based on a block-level source code (systematic) annotation approach.

Formal timing specification

Within this research work, formal timing specifications are based on MULTIC Time Specification Language (MTSL) (Böde et al., 2017), a timing specification language defined within the MULTIC project.1

RT legacy software migration

Fig. 8 depicts (from left to right) the real-time legacy software migration process (described in the following subsections) that ports the RT legacy control software (that complies with the legacy system model defined in Section 3) running on top of the legacy hardware platform to a new (different) hardware architecture.

The migration process consists of four main steps. The first step corresponds to the process of lifting the legacy timing properties (extract legacy timing properties, make

Timing-aware migration assessment

As a proof of concept, the RT legacy software migration approach described in the previous chapter (see Section 6) is used to port ARM Cortex-A9 legacy software to an Intel Atom processor. Therefore, the Xilinx Zynq-7000 System on a Chip (SoC) ZC702 evaluation kit and the MinnowBoard Turbot Dual-Core board have been selected as source and target platforms, respectively. The timing-aware migration assessment describes the evaluation of the implemented block level timing enforcement mechanism as

Conclusion

This research work, first, reasons about the need for a portable legacy software migration solution that preserves the timing as well as the functional behaviour of the retargeted application. In the direction to cover this gap, a RT legacy software migration solution is proposed, which is based on existing static binary translation solution enhanced with a timing enforcement mechanism that at the same time provides means for validating the enforced timing behaviour. The proposed solution is

CRediT authorship contribution statement

Irune Yarza: Conceptualization, Software, Investigation, Writing - original draft, Writing - review & editing. Mikel Azkarate-askatsua: Conceptualization, Validation, Supervision. Peio Onaindia: Validation. Kim Grüttner: Conceptualization, Validation, Supervision. Philipp Ittershagen: Conceptualization, Software. Wolfgang Nebel: Supervision.

Declaration of Competing Interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work contains contributions that have been created in the SAFE4I project, which was funded by the German Ministry of Education and Research (BMBF) under grant agreement no. 01IS17032L. This work has also received funding from the European Community’s Horizon 2020 programme under the UP2DATE project (grant agreement 871465).

Furthermore, the authors would like to thank the Rev.ng tool suit developers for supporting them with the Rev.ng tool and providing them access to their private

Irune Yarza (Galdakao, 1992) received her M.Sc. degree in Advanced Electronic Systems at the University of the Basque Country (Bilbao, Spain, 2016) and her Ph.D. in computer science at the Carl von Ossietzky University of Oldenburg, Germany. Since 2015, she works as a researcher in IKERLAN, where she is part of the Real-Time Systems Group in the Dependable Embedded System Department. Her research topics include real-time embedded systems, with a focus on real-time legacy code migration.

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  • Cited by (0)

    Irune Yarza (Galdakao, 1992) received her M.Sc. degree in Advanced Electronic Systems at the University of the Basque Country (Bilbao, Spain, 2016) and her Ph.D. in computer science at the Carl von Ossietzky University of Oldenburg, Germany. Since 2015, she works as a researcher in IKERLAN, where she is part of the Real-Time Systems Group in the Dependable Embedded System Department. Her research topics include real-time embedded systems, with a focus on real-time legacy code migration.

    Mikel Azkarate-Askatsua (Bergara, 1984) is a Ph.D. in Computer Science by TU-WIEN, (Vienna, Austria, 2012), Master in Embedded Systems by ENSEIRB, (Bordeaux, France, 2008) and Eng. in Electronics by MU (Mondragon, Spain, 2006). He has worked as a researcher in IKERLAN (Mondragon, Spain) since 2008, where he was the Team Leader of the Real-Time Systems Research Group (2016-2018) and he is now the Head of the Dependable Embedded System Department (2018-). He coordinates the SAFEPOWER H2020 project and several other R&D activities on real-time embedded systems, dependable software and industrial security.

    Peio Onaindia (Durango, 1985) is a Master in Software for Embedded Systems by TU Kaiserslautern, (Kaiserslautern, Germany, 2017) and Eng. in Telecommunications by MU (Mondragon, Spain, 2009). He has worked as a researcher in IKERLAN (Mondragon, Spain) since 2010, where he was in charge of developing several real-time embedded systems and he is now the Team Leader of the Real-Time Systems Research Group (2018- ). He coordinates R&D activities on real-time embedded systems and takes part in H2020 projects like SAFEPOWER or DREAMS.

    Kim Grüttner (Delmenhorst, 1979) received his Diploma in computer science in 2005 from Carl von Ossietzky University Oldenburg, Germany and his Ph.D. in computer science in 2015 from the same university. He is Group Manager of the Hardware-/Software Design Methodology Group at OFFIS — Institute for Information Technology in Oldenburg, Germany. His research interests are in the area of Electronic System-Level Designs for safety relevant embedded systems, including specification and design languages, as well as simulation based validation and verification techniques for functionality, time and power consumption.

    Philipp Ittershagen (Quakenbrück, 1986) received his M.Sc. degree in Embedded Systems & Microrobotics at the Carl von Ossietzky University of Oldenburg in 2012 and his Ph.D. in computer science in 2018 from the same university. In 2012, he joined the Hardware/Software Design Methodology group at the OFFIS — Institute for Information Technology in Oldenburg where he is a Senior Researcher since 2015. His research topics include system-level design of embedded real-time systems with a focus on model-based design methodologies and integration flows for mixed-critical systems as well as software performance evaluation in complex Multi-Processor-on-a-Chip platforms.

    Wolfgang Nebel (born 1956) studied electrical engineering at the University of Hannover, Germany. He then obtained his Dr.-Ing. Degree from the Department of Computer Science of the University of Kaiserslautern, Germany. From 1987 to 1993 he worked as a software developer, later as a project manager and finally as head of CAD software development at Philips Semiconductors (now NXP) in Hamburg. In 1993 he was appointed to the Chair of Integrated Circuits at the Department of Computer Science of the Carl von Ossietzky University Oldenburg. In the years 1996 to 1998 he was Dean of the Department of Computer Science and in 2001 and 2002 Vice President of the University of Oldenburg. Since 1998 he has been a member of the board of the OFFIS Institute of Computer Science, an affiliated institute of the University of Oldenburg. Since June 2005 he is chairman of the board of OFFIS. He teaches and researches in the field of novel design methods and tools for embedded systems. He has published more than 200 publications in this field. Prof. Nebel is fellow of the IEEE, member of the National Academy of Science and Engineering, board member of the edacentrum e.V. and member of numerous professional associations and committees. From 2015 to 2017 he was chairman of the EDAA (European Design Automation Association). In January 2015, he became Scientific Vice President of the German Industrial Research Association Konrad Zuse e. V. He is also a member of the steering committee of the German-Turkish Advanced Research Center for ICT (GT ARC).

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