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Evaluating and Constraining Hardware Assertions with Absent Scenarios

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Abstract

Mining from simulation data of the golden model in hardware design verification is an effective solution to assertion generation. While the simulation data is inherently incomplete, it is necessary to evaluate the truth values of the mined assertions. This paper presents an approach to evaluating and constraining hardware assertions with absent scenarios. A Belief-failRate metric is proposed to predict the truth/falseness of generated assertions. By considering both the occurrences of free variable assignments and the conflicts of absent scenarios, we use the metric to sort true assertions in higher ranking and false assertions in lower ranking. Our Belief-failRate guided assertion constraining method leverages the quality of generated assertions. The experimental results show that the Belief-failRate framework performs better than the existing methods. In addition, the assertion evaluating and constraining procedure can find more assertions that cover new design functionality in comparison with the previous methods.

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Authors and Affiliations

  1. State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

    Hui-Na Chao, Hua-Wei Li, Tian-Cheng Wang & Xiao-Wei Li

  2. University of Chinese Academy of Sciences, Beijing, 100049, China

    Hui-Na Chao, Hua-Wei Li, Tian-Cheng Wang & Xiao-Wei Li

  3. Peng Cheng Laboratory, Shenzhen, 518052, China

    Hua-Wei Li

  4. Department of Electrical and Computing Engineering, Portland State University, Portland, OR, 97207, U.S.A.

    Xiaoyu Song

Authors
  1. Hui-Na Chao
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  2. Hua-Wei Li
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  3. Xiaoyu Song
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  4. Tian-Cheng Wang
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  5. Xiao-Wei Li
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Correspondence to Hua-Wei Li.

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Chao, HN., Li, HW., Song, X. et al. Evaluating and Constraining Hardware Assertions with Absent Scenarios. J. Comput. Sci. Technol. 35, 1198–1216 (2020). https://doi.org/10.1007/s11390-020-9708-x

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  • DOI: https://doi.org/10.1007/s11390-020-9708-x

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