Correction to: J Image Video Proc 2020, 31 (2020)
https://doi.org/10.1186/s13640-020-00515-5
Following publication of the original article [1], the authors identified a few errors in the published article.
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1.
Body text contains incorrect sentence - in a simulation, it is possible to analyze the different frequency rates, but it is missing a test generator able to communicate with transceiver. It should be corrected to - in a simulation, it is possible to analyze the different frequency rates, but it is missing a test generator able to communicate with the DUT through the transceiver
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2.
The Figs. 11 and 12 had been inverted. Correct Figs. 11 and 12 with captions should look as per below:
Output from the Omnitek video analyzer
System connection to test the macroblock FPGA input/output chain
The original article [1] has been corrected.
Reference
G. Conti et al., A novel FPGA-based test-bench framework for SDI stream verification. J. Image Video Proc. 2020, 31 (2020). https://doi.org/10.1186/s13640-020-00515-5
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Conti, G., Kyrkou, C., Theocharides, T. et al. Correction to: A novel FPGA-based test-bench framework for SDI stream verification. J Image Video Proc. 2020, 45 (2020). https://doi.org/10.1186/s13640-020-00532-4
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DOI: https://doi.org/10.1186/s13640-020-00532-4