Base solder voids identification of IGBT modules using case temperature
Introduction
As the core of energy conversion system, Insulated-gate bipolar transistor (IGBT) and its modular products are widely used in electric vehicles, rail transit, smart grid, photovoltaic and wind power industry. With the improvement of converter integration, the failure risk of IGBT is increasing, which seriously affects the security of the system [1,2]. In order to reduce failure rate in energy conversion system, it is significant to optimize the condition monitoring and failure identification methods for IGBT module.
Solder layer is one of the most vulnerable parts in multi-layer structure of IGBT module, its stability of connection directly affects junction temperature and device performance [[3], [4], [5]]. Due to the present technical means are difficult to achieve non-invasive junction temperature acquisition, the earliest health assessment mostly depends on the measurement of temperature-sensitive electrical parameters [[6], [7], [8]]. However, this approach does not involve the heat transfer mechanism and has high requirements for the measuring circuit design [6], so the electrical method still face many challenges in non-electrical solder fatigue identification. With the popularity of the finite element simulation software, heat transfer analysis with electro-thermal coupling has become a new direction for solder fatigue identification [[9], [10], [11], [12], [13]]. By using FEM, Gao et al. [10] found that solder fatigue would affect the probability distribution of overall temperature field in IGBT module, and then proposed a solder fatigue identification method based on the statistical characteristics of temperature gradient. But this kind of method belongs to contact measurement, parasitic parameters may be affected. One way to solve this problem is to use the case temperatures below direct copper-clad ceramic bonding (DCB) layer as monitoring parameters to identify solder fatigue. Wang et al. [11,12] studied case temperature tendency in the state of edge crack at base solder layer, they found the central case temperature of IGBT changes with crack growth, so case temperature is an effective parameter to indicate aging degree. Hu et al. [13] further expanded the application of case temperature approach by considering power level and displacement between contact points. Due to the influence mechanism of voids and edge crack is similar, both fatigues would affect the heat transfer in IGBT modules. It means that central case temperature method may also be applicable in voids identification. Compared with edge crack, voids are derived from manufacturing flaws or chemical reaction of solder-alloy [14], distribution of them would be affected by different working conditions [15], it indicates that voids have more irregular distribution, sometimes even small voids would have a serious impact on junction temperature, so it is essential to identify them in early stage.
On the other hand, surface area of base solder layer is much larger than that of chips, heat flow in this area has been fully diffused, considering IGBT and diode are always packaged in pairs, the research of A. S. Bahman et al. [[16], [17], [18]] showed that the thermal coupling effect between chips would interfere temperature distribution of module. Complete voids effect should include variation of both self-thermal diffusion and mutual coupling, it makes voids effect become complex, and indicates that previous identification methods based on case temperature is still not all-round. Consequently, it is necessary to consider the thermal coupling effect in identification process.
This paper proposes a method to identify base solder voids of IGBT module by using case temperature, thermal coupling effect with dynamic condition is fully considered in identification process, and voids effects on the self-thermal diffusion and thermal coupling in case-ambient thermal path are analyzed respectively. The content is arranged as follows. In Section 2, base solder voids identification rules based on the case temperature difference in constant working condition were discussed by analyzing junction/case temperature response with different voids distribution in simulation. In Section 3, a theoretical method to identify base solder voids which is suitable for dynamic load was proposed. It covers theoretical explanation for base solder voids effect on case temperature, temperature-to-thermal resistance conversion and dynamic thermal resistance reference calibration in different power loss ratio by using improved thermal network, real-time identification design based on RLS algorithm. In Section 4, effectiveness of proposed method was proved in simulation. Due to chip solder layer has same area as chip, no place for heat flow to diffuse in this layer, this paper only takes into account base solder voids, and the effect of chip solder voids on case temperature distribution is not considered.
Section snippets
Temperature response with base solder voids
With the radial expansion of base solder fatigue in IGBT module, original thermal behaviors would be altered, which results in the variation of case temperature distribution [11,12,19]. When IGBT chip and diode chip are packaged compactly, the comparison of case temperature distribution in health and void state is shown in Fig. 1. Considering that the central case temperature point below each chip has obvious temperature variation. Therefore, central case temperatures of IGBT and diode are used
Improved thermal network
Thermal network is also called RC network. Its internal parameters are composed of thermal resistance (R) and thermal capacity (C). The existing thermal network include Cauer and Foster model [3,21]. Foster thermal equivalent circuit after adding thermal coupling branch is presented in Fig. 4, Expression of thermal impedance is determined by Eq. (1) [[16], [17], [18]]:where Z(I) and Z(D) represent self-thermal impedance of IGBT and diode, Z(I-D) and Z(D-I) represent
Accuracy verification of FEM
To verify the accuracy of FEM simulation, we compared the transient junction-to-case thermal impedance (Zth) extracted from FEM with test results in Fig. 9, test results are taken from the standard values in datasheet [28]. The comparison shows that the errors in FEM begin to converge since 0.01 s, reason for the poor accuracy of FEM in small time scale is error accumulation from the large number of meshes. At the steady-state, Zth (Rth) errors of IGBT and diode are only 2.11% and 4.55%
Conclusion
A base solder voids identification method by using case temperature has been proposed. According to FEM simulation, junction temperature increases obviously when base solder voids are distributed below the center of chips, and central case temperature would be decreased, so this method compare case temperature to determine the voids damage. In order to define the dynamic case temperature reference, improved thermal network was established for temperature-to-thermal resistance conversion and
CRediT authorship contribution statement
Yuhui Fan: Investigation, methodology, writing – original draft.
Haoyang Cui: Investigation, data curation, writing – original draft.
Zhibin Lou: Data curation, validation, writing – review and editing.
Jiajie Teng: Data curation, methodology, writing – review and editing.
Zhong Tang: Investigation, data curation, validation.
Jianzhong Peng: Supervision, validation.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
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