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Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications

  • Research Article-Electrical Engineering
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Abstract

This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linear-phase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC.

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References

  1. Hannan, M.A.; Islam, M.; Samad, S.A.; et al.: Modulation schemes of SDR for RFID signal transmission performance evaluation. Arab. J. Sci. Eng. 38, 895–900 (2013). https://doi.org/10.1007/s13369-012-0363-6

    Article  Google Scholar 

  2. Ritoniemi, T.; Pajarre, E.; Ingalsuo, S.; Husu, T.; Eerola, V.; et al.: A Stereo audio sigma-delta AD-converter. IEEE J. Solid-State Circ. 29, 1514–1523 (1994)

    Article  Google Scholar 

  3. Hassan, E.E.; Ragheb, H.A.: Design of narrow band decimation filter for sigma delta modulator. Arab. J. Sci. Eng. 36, 1287–1296 (2011). https://doi.org/10.1007/s13369-011-0128-7

    Article  Google Scholar 

  4. Hogenauer, E.: An economical class of digital filters for decimation and interpolation. IEEE Trans. Acoust. Speech Signal Process. 29(2), 155–162 (1981)

    Article  Google Scholar 

  5. Garcia, A.; Meyer-Baese, U.; Taylor, F.: Pipelined Hogenauer CIC filters using field-programmable logic and residue number system. In: Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP ‘98 (Cat. No. 98CH36181), Seattle, WA, USA, vol. 5, pp. 3085–3088 (1998). https://doi.org/10.1109/icassp.1998.678178

  6. Henker, M.; Hentschel, T.; Fettweis, G.: Time-variant CIC-filters for sample rate conversion with arbitrary rational factors. In: ICECS’99. Proceedings of ICECS ‘99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No. 99EX357), Pafos, Cyprus, vol. 1, pp. 67–70 (1999). https://doi.org/10.1109/icecs.1999.812224

  7. Abu-Al-Saud, W.A.; Stuber, G.L.: Modified CIC filter for sample rate conversion in software radio systems. IEEE Signal Process. Lett. 10(5), 152–154 (2003). https://doi.org/10.1109/LSP.2003.810023

    Article  Google Scholar 

  8. Mondal, K.; Mitra, S.: Non-recursive decimation filters with arbitrary integer decimation factors. IET Circuits Devices Syst. 6(3), 141–151 (2012). https://doi.org/10.1049/iet-cds.2011.0240

    Article  Google Scholar 

  9. Laddomada, M.: Comb-based decimation filters for sigma delta A/D converters: novel schemes and comparisons. IEEE Trans. Signal Process. 55(5), 1769–1779 (2007). https://doi.org/10.1109/TSP.2006.890822

    Article  MathSciNet  MATH  Google Scholar 

  10. Milić, D.N.; Pavlović, V.D.: A new class of low complexity low-pass multiplierless linear-phase special CIC FIR filters. IEEE Signal Process. Lett. 21(12), 1511–1515 (2014). https://doi.org/10.1109/LSP.2014.2343212

    Article  Google Scholar 

  11. Dolecek, G.J.; Carmona, J.D.: A new cascaded modified CIC-cosine decimation filter. In: 2005 IEEE International Symposium on Circuits and Systems, Kobe, vol. 4, pp. 3733–3736 (2005). https://doi.org/10.1109/iscas.2005.1465441

  12. Meyer-Baese, U.; Rao, S.; Ramirez, J.; Garcia, A.: Cost-effective Hogenauer cascaded integrator comb decimator filter design for custom ICs. Electron. Lett. 41(3), 158–160 (2005). https://doi.org/10.1049/el:20057000

    Article  Google Scholar 

  13. Serov, A.N., Serov, N.A., Lupachev, A.A.: The application of digital filtration for the active power measurement. In: 2018 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech), St. Petersburg, pp. 88–92 (2018). https://doi.org/10.1109/eexpolytech.2018.8564414

  14. Wang, P.; Zhang, Y.; Yang, J.: Design and implementation of multi-level CIC filter based on FPGA. In: Xhafa, F., Patnaik, S., Tavana, M. (eds.) Advances in Intelligent, Interactive Systems and Applications. IISA Advances in Intelligent Systems and Computing, vol. 885. Springer, Cham (2019). https://doi.org/10.1007/978-3-030-02804-6_72

    Chapter  Google Scholar 

  15. Laddomada, M.: On the polyphase decomposition for design of generalized comb decimation filters. IEEE Trans. Circuits Syst. I Regul. Pap. 55(8), 2287–2299 (2008). https://doi.org/10.1109/TCSI.2008.920136

    Article  MathSciNet  Google Scholar 

  16. Shahana, T.K.; James, R.K.; Jose, B.R.; Jacob, K.P.; Sasi, S.: Polyphase implementation of non-recursive comb decimators for sigma-delta A/D converters. In: 2007 IEEE Conference on Electron Devices and Solid-State Circuits, Tainan, pp. 825–828 (2007). https://doi.org/10.1109/edssc.2007.4450253

  17. Roy, S.; Choudhury, M.; Puri, R.; Pan, D.Z.: Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5), 820–831 (2016). https://doi.org/10.1109/TCAD.2015.2481794

    Article  Google Scholar 

  18. Kogge, P.M.; Stone, H.S.: A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans. Comput. 22(8), 786–793 (1973)

    Article  MathSciNet  Google Scholar 

  19. Held, S.; Spirkl, S.: Fast prefix adders for non-uniform input arrival times. Algorithmica 77, 287–308 (2017). https://doi.org/10.1007/s00453-015-0067-x

    Article  MathSciNet  MATH  Google Scholar 

  20. Penumutchi, B.; Vella, S.; Satti, H: Kogge Stone Adder with GDI technique in 130 nm technology for high performance DSP applications. In: 2017 International Conference On Smart Technologies For Smart Nation (SmartTechCon), Bangalore, pp. 5–10 (2017). https://doi.org/10.1109/SmartTechCon.2017.8358334

  21. Pudi, V.; Sridharan, K.: Low complexity design of ripple carry and Brent-Kung adders in QCA. IEEE Trans. Nanotechnol. 11(1), 105–119 (2012). https://doi.org/10.1109/TNANO.2011.2158006

    Article  Google Scholar 

  22. Koren, Israel: Computer Arithmetic Algorithms, 2nd edn. A. K. Peters, Ltd, Wellesley (2002)

    MATH  Google Scholar 

  23. Esposito, D.; De Caro, D.; Napoli, E.; Petra, N.; Strollo, A.G.M.: Variable latency speculative Han-Carlson adder. IEEE Trans. Circuits Syst. I Regul. Pap. 62(5), 1353–1361 (2015). https://doi.org/10.1109/TCSI.2015.2403036

    Article  Google Scholar 

  24. Oh, H.J.; Lee, Y.H.: Design of discrete coefficient FIR and IIR digital filters with prefilter-equalizer structure using linear programming. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(6), 562–565 (2000). https://doi.org/10.1109/82.847076

    Article  Google Scholar 

  25. Esposito, D.; De Caro, D.; Strollo, A.G.M.: Variable latency speculative parallel prefix adders for unsigned and signed operands. IEEE Trans. Circuits Syst. I Regul. Pap. 63(8), 1200–1209 (2016). https://doi.org/10.1109/TCSI.2016.2564699

    Article  MathSciNet  Google Scholar 

  26. Xuan, G.; Wei-tao, D.: Analysis and design of CIC compensation filter. In: 2011 International Conference on Electric Information and Control Engineering, Wuhan, pp. 3969–3971 (2011). https://doi.org/10.1109/iceice.2011.5778276

  27. Oh, H.J.; Lee, Y.H.: Multiplierless FIR filters based on cyclotomic and interpolated second-order polynomials with powers-of-two coefficients. In: Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, Sacramento, CA, USA, vol. 2, pp. 1449–1452 (1997). https://doi.org/10.1109/mwscas.1997.662357

  28. Molnar, G.; Dudarin, A.; Vucic, M.: Design and multiplierless realization of maximally flat sharpened-CIC compensators. IEEE Trans. Circuits Syst. II Express Briefs 65(1), 51–55 (2018). https://doi.org/10.1109/TCSII.2017.2700081

    Article  Google Scholar 

  29. Engelberg, S.: A more general approach to the filter sharpening technique of Kaiser and Hamming. IEEE Trans. Circuits Syst. II Express Briefs 53(7), 538–540 (2006). https://doi.org/10.1109/TCSII.2006.875326

    Article  Google Scholar 

  30. Teymourzadeh, R.; Othman, M.: VLSI implementation of cascaded integrator comb filters for DSP applications. arXiv preprint arXiv:1808.09369 (2018)

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, K. Ramakrishnan College of Engineering, Tiruchirappalli, India

    A. Abinaya & M. Maheswari

  2. Department of Computer Science and Self-Development Skills, CFY Deanship, King Saud University, Riyadh, Saudi Arabia

    Abdullah Saleh Alqahtani

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  1. A. Abinaya
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  2. M. Maheswari
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  3. Abdullah Saleh Alqahtani
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Correspondence to A. Abinaya.

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Abinaya, A., Maheswari, M. & Alqahtani, A.S. Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications. Arab J Sci Eng 46, 1257–1268 (2021). https://doi.org/10.1007/s13369-020-05016-1

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