Self-Consistent Electro-Thermal Approach for Terahertz Frequency Multiplier Design

Abstract

Solid-state sources consisting of cascaded Schottky diode-based frequency multipliers are commonly used to generate power at millimeter and submillimeter wave bands. In order to achieve increasing power at those frequencies, first-stage frequency multipliers have to handle a large amount of input power and generate enough output power to drive higher frequency multiplication stages. To that end, an appropriate electro-thermal design of multiplier circuits can result in improvement of power-handling capabilities without degradation of conversion efficiency. This work proposes an approach for the design of frequency multipliers where both electrical and thermal considerations are self-consistently taken into account along the optimization of the Schottky diode structure and the circuit layout. The proposed methodology is validated with the design and test of a split-block waveguide single-chip tripler circuit with output frequency in the 225–325-GHz band. Good agreement between predicted performance and measured results is obtained for a wide input power range and different ambient temperatures.

Appendices

Appendix 1: Implementation Details of the Analytical Electro-Thermal Model

The analytical electro-thermal model presented in Section 2 and Fig. 2 is implemented into ADS using its Symbolically Defined Device (SDD) capability. The Schottky diode model incorporates a third terminal connecting the electrical and thermal networks and allowing self-consistent implementation of the temperature dependence of its parameters.

The junction temperature in each anode ($T_{j_{i}}$) is obtained from:

$$ T_{j_{i}}=T_{amb}+{\Delta} T_{sh_{i}} $$

(1)

where T_amb is the ambient temperature and ${\Delta } T_{sh_{i}}$ represents the temperature increment in each anode due to self-heating and thermal coupling among anodes.

Following the topology of the thermal network in Fig. 2, ${\Delta } T_{sh_{i}}$ is related to the stationary dissipated power in each anode ($P_{dis_{i}}$) by a temperature-dependent thermal resistance matrix:

$$ \begin{array}{@{}rcl@{}} \left( \begin{array}{ll} {\Delta} T_{sh_{1}}\\ \quad {\vdots} \\ {\Delta} T_{sh_{N}} \end{array}\right)= \left( \begin{array}{llll} R_{th_{11}}(T_{j_{1}}, T_{amb}) & {\cdots} & R_{th_{1N}}(T_{j_{1}}, T_{amb})\\ \quad \quad \quad {\vdots} & {\ddots} & \quad \quad \quad {\vdots} \\ R_{th_{N1}}(T_{j_{N}}, T_{amb}) & {\cdots} & R_{th_{NN}}(T_{j_{N}}, T_{amb}) \end{array}\right) \cdot \left( \begin{array}{ll} P_{dis_{1}}\\ \quad {\vdots} \\ P_{dis_{N}} \end{array}\right) \end{array} $$

(2)

where N is the number of anodes. The elements $R_{th_{ip}}(T_{j_{i}}, T_{amb})$ take into account the temperature increment in anode i produced by the stationary dissipated power in anode p when no power is dissipated in the rest of anodes [17]:

$$ R_{th_{ip}}(T_{j_{i}}, T_{amb})= \frac{\Delta T_{sh_{i}}}{P_{dis_{p}}} |_{P_{dis_{1}}, \dots , P_{dis_{p-1}}, P_{dis_{p+1}}, \dots , P_{dis_{N}}= 0}.. $$

(3)

It must be remarked that for high excitation frequencies, temperature can be assumed to be time-independent since it is not able to follow variations of the instantaneous dissipated electrical power due to the fact that the thermal time constant is longer than the electrical time constant [35]. However, if thermal dynamics were desired to be taken into account, the thermal network should include instantaneous dissipated power sources and thermal capacitances, which together with thermal resistances define the thermal time constants (τ_th = R_th ⋅ C_th).

On the other hand, regarding the electrical parameters, the voltage-dependent and temperature-dependent junction current is calculated as [36]:

$$ I_{j}(V_{j},T_{j})=I_{sat}(T_{j})\cdot\left[\exp\left( \frac{q\cdot V_{j}}{n\cdot k\cdot T_{j}}\right)-1\right] $$

(4)

where I_sat(T_j) is the temperature-dependent saturation current, V_j the junction voltage, n the ideality factor, k the Boltzmann constant, and q the elementary charge. The temperature-dependent saturation current is defined by [37]:

$$ I_{sat}(T_{j})=A\cdot A^{**}\cdot {T}_{j}^{2}\cdot\exp\left( -\frac{q\cdot{\varPhi}_{b}}{k\cdot T_{j}}\right) $$

(5)

where A is the diode area, A^∗∗ is the effective Richardson constant, and Φ_b is the barrier height. Denoting I_sat(T_nom) as the saturation current at the nominal temperature (T_nom) at which the model parameters are extracted, the saturation current for a given T_j can be calculated as [36]:

$$ I_{sat}(T_{j})=I_{sat}(T_{nom})\cdot\left( \frac{T_{j}}{T_{nom}}\right)^{2} \cdot\exp\left[-\frac{q\cdot{\varPhi}_{b}}{k\cdot T_{j}}\cdot\left( 1-\frac{T_{j}}{T_{nom}}\right)\right]. $$

(6)

In addition, the junction voltage is calculated as:

$$ V_{j}=V_{d}-I_{d}\cdot R_{s}(T_{j}) $$

(7)

where V_d and I_d are the diode voltage and current, respectively, and R_s(T_j) is the temperature-dependent series resistance, which is modeled with the following expression [38]:

$$ R_{s}(T_{j})=R_{s}(T_{nom})\cdot\frac{\beta(T_{nom})}{\beta(T_{j})} $$

(8)

where R_s(T_nom) is the series resistance at T_nom and β(T) for GaAs is [38]:

$$ \beta(T)= 2.135\cdot T^{1.11}\cdot\exp\left( -\frac{T}{31.1}\right)+1.08\cdot \left( \frac{333.3}{T}\right)^{1.6}\cdot 10^{-\left( \frac{45.45}{T}\right)}. $$

(9)

I_sat(T_nom), n, and R_s(T_nom) are obtained from physics-based numerical simulations. The temperature dependence of n and Φ_b is not considered at present.

Appendix 2: Model for the Calculation of Junction Capacitance

The voltage-dependent junction capacitance is determined by:

$$ C_{j}(V_{j})=\frac{dQ_{j}(V_{j})}{dV_{j}} $$

(10)

where Q_j(V_j) is the voltage-dependent junction charge.

Our analytical model includes a sophisticated capacitance model proposed by de Graaff [39], which avoids the singularity given by the theoretical model for fully depleted semiconductor regions when V_j approaches the built-in voltage V_bi [36] and includes the capacitance decrease predicted by physics-based models. It is a modification of the Poon and Gummel’s model [40] that results in a more accurate capacitance description at forward conditions [41]:

$$ C_{j}(V_{j})=\frac{C_{j0}}{(u^{2}+\delta)^{1/2}}\cdot\left( \frac{u+(u^{2}+\delta)^{1/2}}{2}\right)^{1-m} $$

(11)

where C_j0 is the junction capacitance at zero bias (V_j = 0) and is obtained from physics-based numerical simulations, m is the junction grading coefficient (m = 0.5 for abrupt junctions), and u and δ are:

$$ u=1-\frac{V_{j}}{V_{bi}} $$

(12)

$$ \delta=\left[\frac{(1-m)\cdot C_{max}}{C_{j0}}\right]^{-\frac{2}{m}} $$

(13)

where C_max is an adjusting parameter which allows obtaining the proper maximum capacitance value.

It can be remarked that, for a consistent SDD implementation into ADS, this model has to be defined in terms of a voltage-dependent charge function Q_j(V_j) by integrating the capacitance with respect to junction voltage.

Fig. 11

Comparison of different capacitance models including the C-V characteristic simulated with our physics-based numerical model for the diodes used in the designed 225–325-GHz frequency tripler. The values of the parameters utilized in the de Graaff’s capacitance model incorporated into our analytical model are the following: C_j0 = 20.9 fF, V_bi = 0.83 V, m = 0.5, and C_max = 160 fF. The vertical line represents V_bi

Finally, Fig. 11 shows a comparison of different capacitance models including the de Graaff’s model implemented in our analytical approach, the result given by our physics-based numerical model, and the SPICE model, which is the capacitance model included in the ADS diode model.