Simulation of low-noise amplifier with quantized ballistic nanowire channel

Low-noise amplifiers (LNAs) operating under cryogenically cooled conditions, typically below 15 K [1, 2], have found a number of important applications. LNAs are intentionally cooled in order to improve noise performance, which is dependent on electron transport properties and thermal noise in parasitic elements. This is useful in e.g. space applications, such as space communication and astronomy [3, 4]. The temperature of an antenna pointed to outer space is the background temperature of 2.7 K, which is dominated by the receiver noise temperature, unless cryogenically cooled. A second class of applications are high-sensitivity measurements at cryogenic conditions, such as superconductor physics and quantum computing, in which LNAs often must be co-integrated with test structures inside the cryostat [5]. In these cases, a main concern is the power dissipation of the LNA, limited by the cooling system's ability to remove generated heat. In particular, quantum computing applications may in the future require integration of electronics at sub-Kelvin stages in the cryostat, where cooling power is a few hundreds of micro-Watts or lower [5]. Even at higher temperature stages, such as 3 or 4 K, where several Watts of cooling power is available, power budget management will be crucial for dense quantum systems with highly parallelized qubit readout.

State-of-the-art LNAs optimized for cryogenic conditions use InAs/InP high electron mobility transistors (HEMTs) [6], and target a low minimum noise temperature T_min , empirically described as [4]

$$\begin{equation}{T_{{\text{min}}}} \approx 2\frac{f}{{{f_T}}}\sqrt {{R_t}{T_g}{T_d}{G_d}} \end{equation}$$

where R_t = R_i + R_s + R_g, R_i is the intrinsic gate to source resistance, and R_s and R_g are the parasitic source and gate resistances. T_g and T_d are the equivalent temperatures of the gate and the channel respectively. G_d is the output conductance of the device. To minimize T_min, the ratio g_m /√I_DS , the transconductance over the square root of the drain current, must be maximized, which is typically done by tuning the bias point of the transistor. Though state-of-the-art devices obtain T_min of 1.4 K at ambient temperature of 5 K, power dissipation P_DC is in the order of several milli-watt [6]. P_DC determines at what minimum temperature stage in the cryostat the LNA can be operated, i.e. the 3 or 4 K stages for present technology.

In this work, we propose a new type of cryogenic amplifier, a 1D-LNA, which utilizes the properties of a quasi-ballistic MOSFET implementing a 1D (nanowire) channel [7]. Figure 1(a) illustrates an example of this type of device with three parallel lateral nanowires, though it could also be implemented in the vertical direction using vertical nanowires [8]. Such a device will exhibit current steps in the transfer characteristics at cryogenic conditions (also known as quantized conductance) [9, 10]. An amplifier operating at the edge of the first current step exhibits large transconductance and low drain current at a low V_DS of 10–50 mV and provides a strong reduction of DC power dissipation. The characteristics of the 1D-LNA are here determined by simulation using an analytical quasi-ballistic 1D top-of-the-barrier model and small-signal modeling.

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The top-of-the-barrier model describes the operation of a 1D quasi-ballistic transistor by carrier transport between two ideal electron reservoirs, source and drain, through a channel region with one or several conducting sub-bands [7]. The current between the reservoirs is ${I_{DS}}\, = \,{I^ + } - \,{I^ - }$. The forward current is

$$\begin{equation}{I^ + }\, = q{n^ + }{v^ + } = \,q\mathop \smallint {v^ + }D\left( E \right)f\left( {{E_{{F_s}}},E} \right){\text{d}}E\, = \frac{{q{k_B}{T_L}}}{{\pi \hbar }}{\mathrm{\mathcal{F}}_0}\left[ {{\eta _{\mathcal{F}}}} \right]\end{equation}$$

where $\mathcal{F}_n$ is the Fermi–Dirac integral of the nth order, and $\eta_F$ = (E_F —(0))/k_BT_L is the normalized Fermi energy. T_L is the lattice temperature. For the reverse current ${I^ - }$ the Fermi energy is lowered due to the applied drive voltage V_DS by $q{V_{DS}}/{k_B}{T_L}$. Assuming ideal electrostatics, the energy at the top of the barrier, i.e. the bottom of the first sub-band in the channel, is described as

$$\begin{equation}\varepsilon \left( 0 \right) = \, - q{V_{GS}} + \frac{{{q^2}{n_L}}}{{{C_{OX}}}}\end{equation} \tag{ 1 }$$

where n_L is the carrier density and C_OX is the oxide capacitance. (0) is calculated self-consistently from

$$\begin{equation}{n_L} = \frac{{{N_{1D}}}}{2}\left[ {{\mathcal{F}_{ - \frac{1}{2}}}\left( {{\eta _{\mathcal{F}}}} \right) + {\mathcal{F}_{ - \frac{1}{2}}}\left( {{\eta _{\mathcal{F}}} - \frac{{q{V_{DS}}}}{{{k_B}{T_L}}}} \right)} \right]\end{equation} \tag{ 2 }$$

[11, 12]. The drain current is subsequently described as

$$\begin{equation}{I_{DS}} = T\frac{{2q{k_B}{T_L}}}{h}\left[ {{\mathcal{F}_0}\left( {{\eta _{\mathcal{F}}}} \right) - {\mathcal{F}_0}\left( {{\eta _{\mathcal{F}}} - \frac{{q{V_{DS}}}}{{{k_B}{T_L}}}} \right)} \right]\end{equation} \tag{ 3 }$$

where T is the transmission, a transport parameter dependent on the mobility and gate length of the device [13].

Using equations (1)–(3), I_DS can be calculated in a self-consistent manner. The Fermi energy E_F is calculated by solving the Schrödinger equation for a 1D structure. This confinement of the electron wave function in a nanowire results in quantization of the conduction and valence bands into multiple sub-bands. At low temperatures quantized conduction emerges for each energy sub-band, due to the increasing sharpness of the Fermi distribution function [14]. Each sub-band n will contribute to the current as ${I_{DS}} = \mathop \sum \limits_n {I_{DS,n}}$. Figure 1(b) shows the I_DS and g_m for a device with three sub-bands at 30 K and 300 K. In_0.53Ga_0.47As is chosen for the channel material due to the larger Bohr radius compared to Si, which facilitates energy quantization at larger nanowire diameter [15]. The transconductance g_m is independent of the current level at 30 K, as each peak has the same maximum value. The optimal operation point of the proposed 1D-LNA is at a DC gate voltage of the first g_m peak where g_m /√I_DS is maximized. We note that the quantum capacitance C_Q is a result of equation (2), since it is a complete expression of the channel charge density. Its effect is thus included in the calculation of I_DS [16].

Several non-ideal effects are expected. (i) Transmission will be smaller than one, hence quasi-ballistic transport. This will reduce the gain of the transistor. In this work, we use a transmission T = 0.8 for all sub-bands, as has been reported for the In_xGa1_-xAs system [14]. One of the main causes of reduction of the transmission is likely interface defect scattering. (ii) Nanowire size variations will broaden the transconductance peaks and can be modeled as a higher effective temperature of operation. Hence, we chose a simulation temperature of 30 K (unless otherwise stated), while the target ambient temperature is 4 K or below, to more accurately depict expected experimental results. (iii) Line edge roughness will introduce a perturbation to the channel energy bands and can be modeled using atomistic tight binding models but is outside the scope of this work [17, 18]. In general, non-ideal effects will cause a less sharp cutoff of the transmission for energies below the subband edge. However, the increase of g_m in this type of device does not entirely originate from a sharp cutoff but comes from the unique behavior of g_m in a quantized system. Namely, g_m = T2q²/h in the quantum capacitance limit, i.e. a decoupling of g_m from V_DS , as compared to a traditional FET.

For the simulations, we use a cylindrical nanowire with a radius of 5 nm with the first sub-band at 0.2 V. We do not assume a value of the gate length L_G , except that the transmission be T = λ/(λ + L) = 0.8. Figure 1(c) shows the g_m peak shape at different temperatures at V_DS = 10 mV. At lower temperatures, the maximum g_m increases, while the peak width narrows. The maximum value saturates at T2q²/h at sufficiently low temperatures (note that T is the transmission), i.e. g_m decouples from V_DS . This is valid only in the quantum capacitance limit, where the oxide capacitance is much greater than the quantum capacitance. State-of-the-art MOSFETs with scaled gate oxides are expected to operate in this region. In the classical limit, g_m is dependent on V_GS , though not V_DS . This effect is further explored in figure 1(d), showing maximum g_m values versus temperature and V_DS . At 10 mV, the decoupling temperature is about 10 K, while it increases for higher V_DS . As can be seen, lower V_DS leads to a stronger increase from room-temperature to low temperature. This g_m enhancement, g_m(T_L)/g_m (300 K) is shown in figure 2(a) versus temperature and V_DS . The g_m enhancement can be as large as 10.4 for temperatures below 10 K and V_DS = 10 mV. This boost in g_m is unique for the quantized transistor, since for conventional MOSFETs g_m does not typically depend strongly on temperature, except for carrier mobility enhancement due to reduced phonon scattering, which tends to be modest. We note that g_m enhancement in quantized FETs has been experimentally reported, e.g. in [9], showing a factor ∼3 boost at 11 K. We also note that while a complete decoupling of V_DS from g_m is predicted, it is not a necessary feature of the proposed device [19]. A reduction of the V_DS dependence is functionality identical to a boost of g_m at iso-V_DS, which is the important aspect for low-power device operation.

The output conductance, g_d , and the intrinsic voltage gain A_v = g_m /g_d for the first sub-band at V_DS = 10 mV and T_L = 30 K are shown in figure 2(b). The voltage gain at the first g_m peak is 10. At the current plateau, the current is I_DS = TV_DS 2q² /h, thus the output conductance g_d = dI_DS /dV_DS = T2q² /h. This is the same value as g_m , implying that voltage gain cannot be achieved. However, maximum g_d is achieved when I_DS has saturated at the plateau value, while maximum g_m is achieved as I_DS increases to the plateau value. Voltage gain is therefore possible and will depend on temperature and V_DS . Note that g_m and g_d in figure 2(d) have different maximum values due to that 30 K is above the saturation temperature for V_DS = 10 mV, which only impacts the g_m value.

High-frequency characteristics are determined by use of a hybrid-π small signal model [20], as shown in figure 3(a). To obtain realistic simulation results, the values of the parasitic elements are taken from [21], which represents a device structure similar to what is needed to implement the proposed 1D-LNA, i.e. an InGaAs nanowire MOSFET with ∼300 parallel nanowires. We use 300 nanowires with 5 nm radius and 10 nm spacing, and with the parasitic capacitances from [20] normalized to the resulting total gate width. Figure 3(b) shows the associated gain values of the device. The cutoff frequency is f_t = 380 GHz, with a maximum stable gain of 20 dB at 10 GHz, similar values as for the room-temperature device.

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A large value of g_m /√I_DS is desirable in order to minimize T_min. In figure 3(c) we show that the maximum value g_m /√I_DS (16.8 mS/√mA/√µm) for the 1D-LNA is 3x larger than a state-of-the-art cryogenic HEMT [6]. g_m versus I_DS is also shown to confirm that the bias point of minimum noise approximately correlates with that of maximum gain. T_min can also be expected to be strongly reduced compared to a standard HEMT due to the lower power dissipated in the device, which will reduce the drain equivalent noise temperature. However, accurate estimate of T_min will require experimental characterization. In addition, gate leakage can contribute significantly to T_min in fabricated devices. Due to the presence of a gate oxide in the proposed device, the gate leakage is expected to be lower than in a HEMT.

In the 1D-LNA, there is a trade-off between linearity and DC power. The g_m peak width is proportional to both T_L, V_DD and maximum g_m , and will determine the linearity of the amplifier at a given AC input voltage amplitude, V_peak. Next, we study the linearity characteristics of the proposed device. Figure 3(d) shows time-domain simulations of the input bias and output current for a high-bias (V_peak = 30 mV) and a low-bias (V_peak = 5 mV) small-signal input amplitude. The low-voltage signal accurately outputs the sinusoidal input signal (quasi-linear condition), while the high-bias signal is distorted due to the non-linear features of the transfer characteristics. Figure 4(a) shows the amplitude of the harmonic signals as a function of V_peak, relative the fundamental frequency of amplitude 0 dB, at V_DS = 10 mV. The harmonics are obtained from Fourier analysis of the output signal. The amplitudes of the higher harmonics are a measure of the distortion introduced by the g_m characteristics. We observe that at this drive bias, the input bias AC amplitude V_peak should be less than 5 mV to obtain highly linear conditions. This means that the typical 10–100 μV transmon qubit readout signals are well suited for this type of amplifier [22, 23]. Figure 4(b) shows the maximum available power gain as a function of the DC bias point of the input signal V_in, and the drive bias V_DS at 6 GHz (a typical transmon operation frequency). The plateau of the gain indicates the linear region of the amplifier. Since g_m = T2q²/h is independent of V_DS , only the width of the g_m peak increases, not the peak value, which gives rise to this linear region. The physical explanation for this behavior is that an applied V_DS opens a conducting window eV_DS , between the source and drain side Fermi levels, and as the bottom of a subband is swept through the window by V_in, g_m re'dened to correspond to the applied V_DS .

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In Table 1 we compare the cryogenic HEMT [6] to the 1D-LNA for two different drive voltages 10 and 50 mV at temperatures 30 and 100 K respectively. In terms of power dissipation, the 1D-LNA at 10 mV outperforms the HEMT by a factor of 40. We also state a higher level of current gain at 10 GHz, which leads to a 49x better gain to power ratio for the 1D-LNA. The improved performance is mainly due to the g_m boost at low temperatures, but as shown, comes at the price of linearity and is only valid for low-power input signals.

Table 1. Comparing HEMT with 1D-LNA (this work).

Metric	Unit	HEMT @ 5 K [6]	1D-LNA @ 30 K this work	1D-LNA @ 100 K this work
PDC @ IDS = 5 mA	(mW)	2	0.05	0.25
VDS	(mV)	400	10	50
fT	(GHz)	188	380	450
|h21|2 at 10 GHz	(dB)	26	32	33
Gain for power	(B/mW)	13	640	132
$\frac{{{g_m}}}{{\sqrt {{I_{DS}}} }}$ (max)	$\left( {\frac{{mS}}{{\sqrt {mA\mu m} }}} \right)$	5.1	16.8	9.6

We note, finally, that while the transconductance boosting effect has been observed in a suitable device architecture, the remaining experimental challenge is to achieve this effect in a MOSFET with a sufficient number of relatively homogenous parallel nanowires in order to obtain large enough drive current to run the LNA circuit. While we used 300 parallel nanowires for our simulations, this is simply to allow accurate comparison to standard devices. The actual number of needed nanowires will depend on the application and LNA design and could be significantly lower.

We proposed and simulated the concept of a 1D-LNA that uses a quasi-ballistic MOSFET with a scaled nanowire channel showing quantization of energy levels. At cryogenic temperatures, this device achieves up to 10 times boost of the peak transconductance compared to room-temperature. This means that the device can be operated at up to 40 times lower P_DC compared to standard HEMTs, while achieving similar gain and likely reduced noise temperature. P_DC down to 50 μW is possible, indicating the feasibility of operation at sub-Kelvin cryostat temperature stages. While the device shows lower linearity compared to a standard amplifier, it is sufficient for low-power input signals. This type of device shows great promise for the qubit readout in quantum computer applications, where the reduced noise and power can enhance the scalability of the quantum system.

This work was supported by European Union H2020 program SEQUENCE (Grant—871764).