ReviewDeep depletion capacitance–voltage technique for spatial distribution of traps across the substrate in MOS structures
Introduction
As electronic devices are scaled down, the ratio of trap charges to total charges in the substrate channel region is increasing. Therefore, the change in the electrical characteristics of devices due to the trap is increasing. For this reason, characterization and modeling of traps and interface states in MOS structure become increasingly important [1], [2], [3], [4], [5], [6], [7], [8], [9], [10]. As a result, the demand for the characteristics of spatial distribution and energy distribution of the subgap (EV < Et < EC) density of state (DOS) in MOSFETs (metal–oxidesemiconductor field effect transistors) and TFTs (thin-film transistors) with insulated gate structures is increasing [11], [12], [13], [14]. Previous Trap research reports have focused on energy distribution [11], [12], [13], [14]. With non-destructive C-V characterization of vertical trap location in LTPS TFTs and MOSFETs, it allows systematic characterization of the grain boundary location in LTPS TFTs and the trap locations caused by fabrication process and/or degradation through electrical stress in the channel of TFTs and MOSFETs. This allows more intuitive and systematic characterization of spatial location as well as the energy distribution of traps and interface states in FETs. This is expected to be useful for device reliability analysis and provide systematic guidance in the process improvement. Recently there was a report on the separation of the bulk DOS from the interface states [15]. However, this study requires several devices with different substrate thickness assuming a fixed bulk DOS even for devices rather than a single device. In general, both the concentration and the distribution of traps depend strongly on the thickness of the active layer and the manufacturing process. Therefore, it is difficult to accurately extract traps if the device is not a single device in the characterization process. Another report suggests a theoretical model, and extraction is conducted using the calculated results [16], [17]. This method requires a complicated calculation process and inherently carries various error factors.
For comprehensive characterization traps over the energy bandgap, a two-dimensional distribution must be known for space and energy. If there is a technique for separated extraction, as mentioned above, it will be very helpful in the characterization of traps for implementation of robust MOSFETs and TFTs.
Therefore, we report a novel technique for characterizing the vertical spatial distribution of traps for each single MOS device. We combined the capacitance model with experimental capacitance–voltage (C–V) data obtained through the deep depletion mode of bias. Thus, allows extended modulation of the depletion of the substrate suppressing the pinning of the surface potential by the inverted carriers in slow sweep measurement. We expect that the proposed C–V technique for the spatial distribution of traps is useful to the quantitative and reliable analysis of traps linking the electrical characteristics to the process parameters in MOS-based devices.
Section snippets
Experimental
The equivalent capacitance (CG) for the insulated gate structure (MOS and MIS) is modeled by a series connection of the oxide capacitance (Cox: bias-independent) and the substrate capacitance (CS: bias-dependent). The bias-controlled surface potential (ψs)-dependent substrate capacitance (CS(ψs) = CSD(ψs) + Ctrap(ψs)) is a parallel connection of the depletion capacitance (CSD) for the depleted dopants in the substrate with the trap-induced capacitance (Ctrap). In the absence of traps over the
Results and discussion
We employed silicon MOS capacitors with n-type substrate (constant doping: Nsub = ND = 2.6 × 1019 [cm−3]) with W/L = 10/10 [μm/μm] and tox = 20 [nm] for experimental application of the proposed C–V technique. We first obtained experimental C–V data for the device through fast sweep mode of measurement for extended modulation of effective trap depth the substrate as shown in Fig. 2(a). The VG-dependent surface potential (ψS(VG)) is mapped from the experimental C–V data through
Conclusion
In this work, a C-V technique is reported for characterization for the spatial distribution of traps across the substrate in MOS structures. A fast sweep mode of C-V measurement was employed for deep and extended depletion of the substrate. From the deviation of the experimental C-V data with traps from the ideal C-V curve, the spatial distribution of the traps across the substrate from the Si/SiO2 interface is obtained through the equivalent capacitance model. Using the deep depletion mode C-V
Declaration of Competing Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF) Grant funded by the Korean Government (MSIP) (No. 2017R1A2B4007820 and No.2016R1A5A1012966), and the CAD software was supported by Silvaco and IC Design Education Center.
Han Bin Yoo received the M.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree with the Department of Electrical Engineering.
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Cited by (1)
Han Bin Yoo received the M.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in 2020, where he is currently pursuing the Ph.D. degree with the Department of Electrical Engineering.
Jintae Yu received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in 2019, where he is currently pursuing the M.S. degree with the Department of Electrical Engineering.
Haesung Kim received the B.S. degree in electrical engineering from Kookmin University, Seoul, Korea, in 2020, where he is currently pursuing the M.S. degree with the Department of Electrical Engineering.
Ji Hee Ryu is currently pursuing the B.S. degree with the Department of Electrical Engineering from Kookmin University, Seoul, Korea.
Sung-Jin Choi received the M.S. and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2012. He is currently an Associate Professor with the School of Electrical Engineering, Kookmin University, Seoul, Korea.
Dae Hwan Kim (M’08–SM’12) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1996, 1998, and 2002, respectively. He is currently a Professor with the School of Electrical Engineering, Kookmin University, Seoul, Korea. His current research interests include nanoCMOS, oxide and organic thin-film transistors, biosensors, and neuromorphic devices.
Dong Myong Kim (S’86–M’88) received the B.S. (magna cum laude) and M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1986 and 1988, respectively, and the Ph.D. degree in electrical engineering from the University of Minnesota, Twin Cities, MN, USA, in 1993. He has been with the School of Electrical Engineering, Kookmin University, Seoul, since 1993.
- 1
Contributed equally to this work.