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High-Efficient, Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications

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Abstract

Size reduction in complementary metal–oxide–semiconductor integrated circuits (ICs) is a challenge. Carbon nanotube field effect transistor (CNTFET) technology with advantages such as low power, high mobility, and ballistic transmissions is an alternative. Based on the standard 32 nm CNTFET technology, a new 23-transistor full adder cell is proposed with combining advantages of gate diffusion input and transmission gate techniques, which are low power and full swing. Owing to small number of transistors and internal nodes, the delay time and activity factor decreased to 13.5τ. Simulations of critical parameters variations like VDD, temperature, and fan-out expose better performance of the proposed cell. Investigating the process voltage temperature with Monte Carlo simulation verified better stability, immunity, and tolerability of the cell in comparison with well-known full adder cells. Suggested full adder cell was implemented in 4:2 compressor with 9.0298 fJ of power delay product and minimum area occupation among the references. Based on real chip measurements, total die area occupation for proposed full adder and compressor is 0.505 µm2 and 1.092 µm2, respectively. Proposed circuits were applied to an 8-bit subtractor for orthopantomogram image processing to detect tooth core build up and restored with dental filling in order to maintain a crown restoration. Merits of proposed circuits both in IC design and image processing make these circuits suitable choice for bioelectronics chips.

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References

  1. E. Abiri, Z. Bezareh, A. Darabi, The optimum design of RAM cell based on the modified-GDI method using Non-dominated Sorting Genetic Algorithm II (NSGA-II). J. Intell. Fuzzy Syst. 32, 4095–4108 (2017)

    Article  Google Scholar 

  2. E. Abiri, A. Darabi, M.R. Salehi, A. Sadeghi, Optimized gate diffusion input method-based reversible magnitude arithmetic unit using non-dominated sorting genetic algorithm II. J Circuits, Syst Signal Process (2020). https://doi.org/10.1007/s00034-020-01382-1

    Article  Google Scholar 

  3. E. Abiri, A. Darabi, S. Salem, Design of multiple-valued logic gates using gate-diffusion input for image processing applications. Comput. Electr. Eng. 69, 142–157 (2018)

    Article  Google Scholar 

  4. M. Aguirre-Hernandez, M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans. Very Large Scale Integr. Syst. 19(4), 718–721 (2011)

    Article  Google Scholar 

  5. M. Ahmadinejad, M. Moaiyeri, F. Sabetzadeh Farnaz, Energy and area efficient imprecise compressors for approximate multiplication at nanoscale. AEU Int. J. Electron. Commun. 110, 152859 (2019)

    Article  Google Scholar 

  6. M. Amini-Valashani, M. Ayat, S. Mirzakuchaki, Design and analysis of a novel low power and energy-efficient 18T hybrid full adder. Microelectron. J. 74, 49–59 (2018)

    Article  Google Scholar 

  7. H. Basireddy, K. Challa, T. Nikoubin, Hybrid logical effort for hybrid logic style full adders in multistage structures. IEEE Trans. Very Large Scale Integr. Syst. 27(5), 1138–1147 (2019)

    Article  Google Scholar 

  8. C.H. Chang, J. Gu, M. Zhang, A review of 0.18-μm full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(6), 686–695 (2005)

    Article  Google Scholar 

  9. J. Deng, H.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron. Devices 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  10. J. Deng, H.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron. Devices 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  11. Y. S. Eberhart, Particle swarm optimization: developments, applications and resources, in Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546), Seoul, South Korea vol. 1 (2001), pp. 81–86

  12. F. Ebrahimi-Azandaryani, O. Akbari, M. Kamal, A. Afzali-Kusha, M. Pedram, Block-based carry speculative approximate adder for energy-efficient applications. IEEE Trans. Circuits Syst. II Express Briefs (2019). https://doi.org/10.1109/tcsii.2019.2901060

    Article  Google Scholar 

  13. M. Fonseca, E. Costa, J. Martins, Design of power efficient butterflies from Radix-2 DIT FFT using adder compressors with a new XOR gate topology. Analog Integr. Circuits Signal Process. 73, 954 (2012). https://doi.org/10.1007/s10470-012-9952-2

    Article  Google Scholar 

  14. A. Franklin, C. Zhihong, Length scaling of carbon nanotube transistors. Nat. Nanotechnol. 5, 858–862 (2010). https://doi.org/10.1038/nnano.2010.220

    Article  Google Scholar 

  15. S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style. IEEE Trans. Very Large Scale Integr. Syst. 14(12), 1309–1321 (2006)

    Article  Google Scholar 

  16. R. Gupta, A. K. Rana, Comparative study of digital inverter for CNTFET & CMOS technologies, in Nirma University International Conference on Engineering (NUiCONE), Ahmedabad (2013), pp. 1–5

  17. D. Hodges, H. Jackson, R. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd edn. (McGraw-Hill, incorporated, New York). ISBN-13: 978-0072283655

  18. J. Huang, M. Zhu, P. Gupta, Sh. Yang, S. Rubin, G. Garret, J. He, A CAD tool for design and analysis of CNFET circuits, in IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), Hong Kong (2010), pp. 1–4

  19. J. Huang, M. Zhu, S. Yang, P. Gupta, W. Zhang, S. Rubin, G. Garretón, J. He, A physical design tool for carbon nanotube field-effect transistor circuits. ACM J. Emerg. Technol. Comput. Syst. 8, 1–20 (2012). https://doi.org/10.1145/2287696.2287708

    Article  Google Scholar 

  20. C. Li, Y. Chen, T. Chang, J. Chen, A probabilistic estimation bias circuit for fixed-width booth multiplier and its DCT applications. IEEE Trans. Circuits Syst. II Express Briefs 58(4), 215–219 (2011)

    Article  Google Scholar 

  21. J.J. Liang, A.K. Qin, P.N. Suganthan, S. Baskar, Comprehensive learning particle swarm optimizer for global optimization of multimodal functions. IEEE Trans. Evol. Comput. 10(3), 281–295 (2006)

    Article  Google Scholar 

  22. J. Lin, Y. Hwang, M. Sheu, C. Ho, A novel high-speed and energy efficient 10-transistor full adder design. IEEE Trans. Circuits Syst. I 54(5), 1050–1059 (2007)

    Article  Google Scholar 

  23. M.H. Moaiyeri, R. Faghih Mirzaee, K. Navi, A. Momeni, Design and analysis of a high-performance CNFET-based full adder. Int. J. Electron. 99, 113–130 (2012)

    Article  Google Scholar 

  24. E. Mollick, Establishing Moore’s Law. IEEE Ann. Hist. Comput. 28(3), 62–75 (2006)

    Article  MathSciNet  Google Scholar 

  25. A. Morgenshtein, A. Fish, I.A. Wagner, Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans. Very Large Scale Integr. Syst. 10(5), 566–581 (2002)

    Article  Google Scholar 

  26. A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, A. Fish, Full-swing gate diffusion input logic—case-study of low-power CLA adder design. Integr. VLSI J. 47, 62–70 (2014)

    Article  Google Scholar 

  27. H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans. Very Large Scale Integr. Syst. 26(8), 1481–1493 (2018)

    Article  Google Scholar 

  28. V. Niranjan, A. Singh, A. Kumar, Dynamic threshold MOS transistor for low voltage analog circuits. Int. J. Sci. Res. Eng. Technol. (IJSRET), India. ISSN: 2278 (2014)

  29. D. K. Patel, R. Chouksey and M. Saxena, Design of fast FIR filter using compressor and Carry Select Adder. In: 2016 3rd International Conference on Signal Processing and Integrated Networks (SPIN), Noida, 460-465, 2016

  30. A. Pishvaie, G. Jaberipur, A. Jahanian, Improved CMOS (4;2) compressor designs for parallel multipliers. Comput. Electr. Eng. 38(6), 1703–1716 (2012)

    Article  Google Scholar 

  31. D. Radhakrishnan, Low-voltage low-power CMOS full adder. IEE Proc. Circuits Devices Syst. 148(1), 19–24 (2001)

    Article  Google Scholar 

  32. A. Ratnaweera, S.K. Halgamuge, H.C. Watson, Self-organizing hierarchical particle swarm optimizer with time-varying acceleration coefficients. IEEE Trans. Evol. Comput. 8(3), 240–255 (2004)

    Article  Google Scholar 

  33. Y. Safaei Mehrabani, M. Eshghi, Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. IEEE Trans. Very Large Scale Integr. Syst. 24(11), 3268–3281 (2016)

    Article  Google Scholar 

  34. Y. Safaei Mehrabani, M. Eshghi, A symmetric, multi-threshold, high-speed and efficient-energy 1-bit full adder cell design using CNFET technology. Circuits Syst. Signal Process. (2014). https://doi.org/10.1007/s00034-014-9887-1

    Article  Google Scholar 

  35. B. Silveira, G. Paim, B. Abreu, M. Grellert, C. Diniz, E. Costa, S. Bampi, Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding, in 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi (2017), pp. 409–493

  36. S.K. Sinha, S. Chaudhury, Impact of temperature variation on CNTFET device characteristics, in 2013 International Conference on Control, Automation, Robotics and Embedded Systems (CARE) (2013), pp. 1–5

  37. S.K. Sinha, K. Kumar, S. Chaudhury, CNTFET: the emerging post-CMOS device, in 2013 International Conference on Signal Processing and Communication (ICSC), Noida (2013), pp. 372–374

  38. M. Tan, G. Lentaris, G. Amaratunga, Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET. Nanoscale Res. Lett. 7(1), 467 (2012)

    Article  Google Scholar 

  39. A. Torkzadeh Mahani, P. Keshavarzian, A novel energy-efficient and high speed full adder using CNTFET. Microelectron. J. 61, 79–88 (2017)

    Article  Google Scholar 

  40. J.P. Uyemura, Circuit design for CMOS VLSI (1992). https://doi.org/10.1007/978-1-4615-3620-8

  41. N.H.E. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective (Addison-Wesley, Reading, 1988)

    Google Scholar 

  42. N.H.E. Weste, D. Harris, CMOS VLSI design: A circuits and systems perspective, 4th edn. (Addison-Wesley Publishing Company, United States, 2010). ISBN:978-0-321-54774-3

  43. Z. Yang, J. Han, F. Lombardi, Transmission gate-based approximate adders for inexact computing, in Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15) (2015), pp. 145–150

  44. K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, A. Shimizu, A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. IEEE J. Solid-State Circuits 25(2), 388–395 (1990)

    Article  Google Scholar 

  45. M. Zhang, J. Gu, C.H. Chang, A novel hybrid pass logic with static CMOS output drive full-adder cell, in Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS ‘03, Bangkok (2003), pp. V–V

  46. R. Zimmerman, W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circuits 32(7), 1079–1090 (1997)

    Article  Google Scholar 

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Sadeghi, A., Shiri, N. & Rafiee, M. High-Efficient, Ultra-Low-Power and High-Speed 4:2 Compressor with a New Full Adder Cell for Bioelectronics Applications. Circuits Syst Signal Process 39, 6247–6275 (2020). https://doi.org/10.1007/s00034-020-01459-x

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